XilinxIO.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, February 14, 1990 5:21:06 pm PST
DIRECTORY Core, CoreClasses, CoreFlat, RefTab, Rope, Sisyph, SymTab;
XilinxIO: CEDAR DEFINITIONS = BEGIN
ROPE: TYPE = Rope.ROPE;
LOR: TYPE = LIST OF ROPE;
Placement
Axis: TYPE = {ax,ay};
Loc: PROC [cx: Sisyph.Context, x, y: INT] RETURNS [trash: NAT ← 0];
Set: PROC [cx: Sisyph.Context, x, y: INT, axis: Axis ← ax] RETURNS [trash: NAT ← 0];
Seq: PROC [cx: Sisyph.Context, axis: Axis, startIndex, orthogonalIndex: NAT, delta: INT ← 1] RETURNS [trash: NAT ← 0];
IO
SaveCellType: PROC [cellType: Core.CellType, fileName: ROPE ← NIL] RETURNS [multiplyDriven: LIST OF ROPE ← NIL];
fileName=NIL => fileName ← Rope.Cat[CoreOps.GetCellTypeName[cellType], ".xnf"]
RegisterPrimitive: PROC [coreName: ROPE, proc: TranslateProc, data: REF ANY ← NIL];
MakeBindList: PROC [public: Core.Wire] RETURNS [bindlist: BindList ← NIL] ;
GetParameters: PROC [symbol: Symbol, instance: CoreClasses.CellInstance];
CreateSignal: PROC [circuit: FlatCircuit, name: ROPE ← NIL] RETURNS [signal: Signal];
CreateBoundSignal: PROC [wire: Core.Wire, circuit: FlatCircuit, root: Core.CellType, flatWireToSignal: RefTab.Ref, bindings: RefTab.Ref, flatCell: CoreFlat.FlatCellTypeRec] RETURNS [signal: Signal];
AddSymbol: PROC [circuit: FlatCircuit, name, type: ROPE, bindings: PinSignals] RETURNS [symbol: Symbol];
MakeSymbol: PROC [name, type: ROPE, bind: BindList, pins: Pins, circuit: FlatCircuit, root: Core.CellType, flatCell: CoreFlat.FlatCellTypeRec, flatWireToSignal, bindings: RefTab.Ref, parameters, configs: LOR ← NIL] RETURNS [symbol: Symbol];
PinRecListToPinList: PROC [pins: PinRecList] RETURNS [refPins: Pins ← NIL];
Types
BindList: TYPE = LIST OF RECORD[wire: Core.Wire, name: ROPE];
Primitive Data Base
Primitive: TYPE = REF PrimitiveRec;
PrimitiveRec: TYPE = RECORD [
translate: TranslateProc,
data: REF ANY];
TranslateProc: TYPE = PROC [circuit: FlatCircuit, root, cell: Core.CellType, instance: CoreClasses.CellInstance, name: ROPE, flatCell: CoreFlat.FlatCellTypeRec, flatWireToSignal, bindings: RefTab.Ref, part2000: BOOL, data: REF ANY];
Flattened Circuit
FlatCircuit: TYPE = REF FlatCircuitRec;
FlatCircuitRec: TYPE = RECORD [
nameCount: INT ← 0,
nameTable: SymTab.Ref ← NIL,
symbols: Symbols ← NIL,
signals: Signals ← NIL,
partType: ROPE ← NIL];
Symbols: TYPE = LIST OF Symbol;
Symbol: TYPE = REF SymbolRec;
SymbolRec: TYPE = RECORD [
name: ROPE ← NIL,
type: ROPE ← NIL,
connections: SymbolSignalPins ← NIL,
parameters: LOR ← NIL,
configs: LOR ← NIL];
SymbolSignalPins: TYPE = LIST OF SymbolSignalPin;
SymbolSignalPin: TYPE = REF SymbolSignalPinRec;
SymbolSignalPinRec: TYPE = RECORD [
symbol: Symbol ← NIL,
signal: Signal ← NIL,
pin: Pin ← NIL,
parameters: LOR ← NIL];
Signals: TYPE = LIST OF Signal;
Signal: TYPE = REF SignalRec;
SignalRec: TYPE = RECORD [
name: ROPE ← NIL,
connections: SymbolSignalPins ← NIL,
pin: ROPE ← NIL, -- NIL => not forced
unbonded: BOOL ← FALSE,
parameters: LOR ← NIL];
some connections' pin.physicalPin = TRUE causes an EXT record to be emitted using unbonded, pin, and parameters
all connections' pin.physicalPin = FALSE and parameters#NIL causes a SIG record to be emitted
PinSignals: TYPE = LIST OF PinSignalRec;
PinSignalRec: TYPE = RECORD [
pin: Pin ← NIL,
signal: Signal ← NIL];
Pins: TYPE = LIST OF Pin;
PinRecList : TYPE = LIST OF PinRec;
Pin: TYPE = REF PinRec;
PinRec: TYPE = RECORD [
coreName: Rope.ROPE,
xilinxName: Rope.ROPE,
direction: InOrOut,
physicalPin: BOOL ← FALSE,
tristate: BOOL ← FALSE,
invert: BOOL ← FALSE];
InOrOut: TYPE = {In, Out};
END.