Every electronic system must be tested during the manufacturing cycle to ensure that it meets specifications. Digital electronic system specifications are comprised of power supply, temperature, timing and function specifications. Power supply and temperature specifications are limited to the specification of minimum and maximum values. Timing and function specifications are much more complex. Timing specifications define the relative placement in time of voltage transitions between the zero and one values. Function specifications define the output values over time given a set of input values at specified times. As a device operates, the timing specifications determine the details, while the function specifications determine the operation over longer periods of time.

General purpose digital test systems make use of this split between timing and function specification in their design. Their implementation is divided into the data generator section, which implements the function specification, and the pin electronics section, which implements the timing specification. A vector consists of the values to be forced on the inputs of the device under test, or DUT, and the values to be checked on the outputs. Time is divided into periods, called cycles. The test system stores one vector per cycle. During each cycle, the pin electronics section is responsible for combining the contents of the current vector with the timing information to produce the waveforms for stimulating the DUT and measuring the result.

Digital test systems have, in the past, been divided into two major categories: printed circuit board testers and integrated circuit testers. The reason for this dichotomy is the difference in scale between the two implementation techniques. Printed circuit boards are sufficiently large (physically) that it is possible to probe the board internally and ensure that it is constructed correctly by checking the individual traces. In contrast, integrated circuits are so small that it is not possible to probe them internally; only the pins can be accessed. All information must pass through these pins, both for test purposes, and in actual operation. Some modern printed circuit boards have become sufficiently dense that it is no longer possible to adequately test them via probes on their surface. Instead, test techniques previously reserved for integrated circuit testing must be applied to them.

All complex electronic system design makes heavy use of simulation to ensure that a design is correct before the time consuming, expensive process of fabrication is begun. Hardware modeling uses a physical device, rather than a software program, to model a high complexity device in such a simulation. This has become important as the complexity of components has risen to such a level that writing complete, accurate models in a timely fashion, i.e. before the device is obsolete, has become impossible.

If we look at the basic functionality of a hardware modeller we see that it consists of the same data generator and pin electronics sections as a digital test system. The only difference is that a hardware modeller is interrogating the DUT for its response rather than checking that the response matches a predetermined value. It is assuming that the DUT is correct rather than checking it for correctness.

In addition to the electronic portion of a test system there must be a mechanical portion which holds the physical device. The type of testing being performed, either design verification or production, determines the mechanism.

The mechanical system is only one of the two interfaces which a test system must consider. The other is the interface to the design or test engineer. How does the engineer describe the correct operation of a device so that the tester can check it? How does the engineer relate failures discovered by the tester back to his original design description?

The engineer has already described the correct operation of the device once in order to simulate the design prior to fabrication. This same description forms the nucleus of the vectors and timing description which the tester requires.

Typically both the design description and the description of correct operation are available on an engineering workstation. The engineer would like to control the tester and interpret the tester results in the same fashion as the simulation was controlled.

This is defined as getting the current channel chip ready to put into a system, not to build a system. Proof of concept from a research point of view has been completed. A great deal of work remains to document the specifications of the channel chip and to ensure that it meets those specifications.

Some of the things which must be done include:

The advantages of redesigning the channel chip are discussed in detail in [Gasbarro2]. Improvements can be made by increasing density or capability. Unless DUT pin counts exceed 256, increased density only results in a modest decrease in system price. Thus increased capability should be the target of a redesign.

Three areas of capability improvement are possible: more flexible channel electronics, increased vector RAM size, and higher performance DUT drive and sense circuits. High performance DUT drive and sense is substantially improved if an advanced technology such as Bi-CMOS is available. This would allow the channel chip to dominate the characteristics, except for vector depth, of every tester currently on the market, even those costing several million dollars.

The hardware modelling application requires sampling the response rather than comparing against a predicted result. One could just predict all zero and then use the error buffer for determining which values were actually ones but that limits the number of unknown cycles to the depth of the error buffer.

All of the chip development items mentioned in section 5.1 must be performed for the new device.

This section assumes that all of the work in section 5.1 has been completed and that the goal is to produce a system which can be placed directly into the hands of integrated circuit designers.

An interface must be built to transfer test data from any CAD environment into the test environment. The detailed work for the most popular CAD environments must be completed and the interface documented so that any weird systems can be interfaced by the customer. OEM agreements with the major CAD houses would ease this problem substantially and allow a much higher quality solution.

All of the standard test system software must be written. This includes shmoo plotting and other failure analysis software.

A salable implementation of the computer interface and timing generator must be included in the printed circuit board design effort. This may require the design of an ASIC.

Large quantities of high quality documentation must be written, marketing and sales support established, customer hot lines set up, etc, etc.

Suppose that the intention is to move into the market as soon as possible with a redesigned channel chip and its associated evaluation board.

Development assumptions:

Market assumptions:

These assumptions require an investment of about $750K through third quarter 1990 and start producing a return by third quarter 1991, with return ramping up quickly through third quarter 1993, followed by a slight drop as pent up demand is satisfied, and finally reaching a steady state sometime in 1994.

Ways to go about getting the numbers:

Also need to talk to potential customers, i.e. ASIC designers, production test people. Get Xerox people in to look at the thing, or take it to them. Road trip to El Segundo, Bob St. John. Find out relative importance of features.