Introduction This document is the theory of operation for the SBus board portion of the spread spectrum digital radio communications link. It assumes that the reader has the schematics available and directly references signal and cell names within them. The majority of this document describes the design of the logic contained within the Xilinx field programmable gate array. Additional sections describe the physical implementation, both wirewrapped and pcb, simulation test suite, development software, and areas to investigate. The SBus board has three basic functions: data handling, transmitter enable, and receive code synchronization. The data handling is complicated somewhat by the receive code synchronization which requires that 0101 sequences appear frequently in the received data stream. To accomplish this an 8-10 code is used so that such sequences appear with a guaranteed minimum frequency, independent of packet length. There are three sources of time in the design, the SBus clock and the receive and transmit crystals. However, there are four synchronous timing domains in the design: SBus, main clock, receive code generation, and transmit code generation. The vast majority of the logic is run by the 5 MHz main clock, which is the 20 MHz receive clock divided by 4. The receive and transmit code generation clocks only clock the flip-flops in the respective code generators. The SBus clock only clocks the control path from nSel combined with nAS to Ack. No simulation or timing analysis has been performed to guarantee that all of the combinatorial paths inside of the Xilinx will meet the setup times required by the flip-flops. However the clock is so slow for the vast majority of the logic that it seems extremely unlikely that this is a source of difficulty and, in any case, no problems which could be ascribed to timing failures have been noticed. Cell Descriptions Cell SSCtl is the top level schematic for the logic which is contained within the Xilinx. Cell PCB contains the board level schematics. The theory behind the small amount of circuitry contained on the PCB is covered in the Receive cell description. Bits are numbered high order to low order in all cells except the PCB cell, where they are numbered low order to high order. SSCtl This cell forms the basic decomposition of the design between the bus interface, transmit logic, and receive logic. The ErrorGen cell was grafted on later to allow the capture of errors in which the transmitter sends a byte but the receiver fails to recognize the start pattern. This does not catch the other dominant failure mode, which is proper start pattern recognition followed by corrupted data. It would be fairly straightforward to further distort the division between transmit and receive so that this other failure mode is caught. All of the public signals flowing into the SBusInterface are synchronous to the SBus clock. RegAdr is also synchronous to the SBus clock, although its setup and hold times relative to the other internal interface signals are so large and its usage is such that this distinction can safely be ignored. All of the remaining signals are synchronous to CK, except as noted below. The next section provides a functional pin description of the Xilinx as programmed for this application. The SBus interface signals are not documented here. The reader should refer to the SBus Specification Rev A for their documentation. The signals specific to the Xilinx are also not documented; refer to the Xilinx programmable gate array data book. Non SBus pins TxClock (input) - nominally a 10 MHz clock. It actually must be slightly less than 10 MHz, e.g. 9.99981 MHz. Actual acceptable range for this clock has yet to be determined, see the Areas to Investigate section. TxCode (output) - pseudorandom code used to spread the transmit signal. Synchronous with TxClock. For details look in the CodeGen cell description. TxData (output) - transmit data. Note that this is synchronous with CK, which is divided down from the receive clock, not the transmit clock. TxEnb (output) - transmit enable. Error (output) - loopback error. Single pulse one CK period long each time transmit start is asserted without a matching receive start. For details look in the ErrorGen cell description. ToInt (output) - to integrator. Single pulse one CK period long each time an invalid pair of transitions is detected. RxCode (output) - pseudorandom code used to despread the received signal. RxClock (input) - nominally a 20 MHz clock. It actually must be slightly more than 20 MHz, e.g. 20.00036 MHz. Actual acceptable range for this clock has yet to be determined, see the Areas to Investigate section. RxData (input) - receive data. Synchronous with the RxClock of whichever transmitter has currently captured the receiver. Random noise if there is no such transmitter. SlipEnb (input) - slip enable. When high this allows the clock generating the receive code to have half cycles deleted so that it can be synchronized with the transmit code of the current transmitter. When low no such deleteions can occur. This is useful when adjusting the integrator threshold. CodeLock (input) - this is the output of the thresholded integration node. AmpLock (input) - lock detection output from receiver. SamClk (output) - phase lock loop clock. SamData (output) - phase lock loop data. SBusInterface Mostly this block simply buffers the SBus data and address wires into the internal logic. It also provides the control signals necessary for byte reads and writes. The control path is an open-ended shift register style sequencer. Each time a falling edge on nAS is detected while nSel is asserted a one is shifted into the beginning of the sequencer. This one is synchronized with CK and then, if the bus size is correct, asserts either RegRead or RegWrite for approximately one CK cycle. The trailing edge of this CK synchronous timing pulse is then synchronized back into the SBus clock timing domain and the proper acknowledgement is generated. At the bottom of the cell there is a shift register which has a constant one as its input. Its purpose is to ensure that the nAck wires are not asserted during the startup transient which occurs directly after programming the Xilinx. It is extremely important that the delay from CK to nAck tristate enable be as short as possible. To accomplish this the tristate controls are mapped into a specific CLB and the path from them to the pad tristate enables are marked as critical. Another approach, not implemented here, is to bracket the time periods during which the nAck wire is transitioning with tristate enable and then merely toggling the data inputs of the tristate devices. The combination of nBG and nReset is used to produce a known zero without using Gnd as the source. The tristate devices to which this known zero is tied must be present so that the Xilinx software won't assign these pads to some random flip-flop when the pads are physically attached to the corresponding SBus signals. Using Gnd as the known zero causes the Xilinx software to toss out the tristate devices as obviously useless. AckFlop This cell controls the tristate enables for acknowledgement. The A, B, and D inputs combine the bit shifting through the sequencer with the size information and startup transient suppression to enable the driver. The E input turns off the tristate enable two SBus clock cycles after enabling it. The K input must be the SBus clock. Transmit Both data and control are combined in this cell. The data path takes the byte presented by the buffered SBus data wires, combinatorially recodes it into 10 bits and then drops it into a shift register. The first bit of the the output shift register is broken out into discrete gates because otherwise the Xilinx software complains about the first SerialIn bit being set to a constant. The wires between the encoder and the shifter are reversed so that the bit pattern can be read off of an oscilloscope trace, left to right, most significant bit first. The controller is a closed loop shift register style sequencer. After device programming all flip-flops are set to zero. One flip-flop in the sequencer is surrounded by inverters so that the initial zero appears as a one. This sequencer shifts at the bit rate, rather than at the basic CK rate, so all the flip-flops have enables which are asserted once per bit time. Writing a byte into the output shift register also causes a request for transmission to be posted in the transmit busy flip-flop. When a request is posted, and the idle pattern has been sent for at least 10 bits, and the last bit sent was a one, then the controller sends the start of packet sequence, which consists of 4 additional ones. After the controller has sent the start of packet sequence it transmits the 10 bits of the current byte and then returns to sending the idle pattern. SBus register reads are implemented by chaining multiplexors rather than using tristate drivers. This is done because the Xilinx architecure and place and route software does not work well with tristate drivers. This block has a single register which can be read. The high order bit is the transmit busy bit. The next bit is the transmit enable bit. Only the transmit enable bit can be directly written. ShiftOutBit This cell implements a standard parallel load shift register with load and shift controls. It is CLBMapped in an effort to help the placement software find a good solution quickly. CodeGen This cell generates a pseudorandom sequence which is used for spreading and despreading the transmitted signal. It is a maximal length sequence for 6 bits, or 63. The illegal state, which is all zeroes, is detected and a one injected, to start the sequence generator. Encode8to10 and Decode10to8 In order to guarantee that 0101 sequences occur sufficiently often to allow loss of lock to be detected, the transmitted byte is recoded from 8 bits into 10 bits. The table below shows the mapping between the 8 bit and 10 bit codes. The first column lists the 8 bit patterns taken in to be transmitted or to be produced after reception. The second column lists the 10 bit patterns which are actually transmitted and received by the radio. The third and fourth columns are similiar but they list exceptions to the general rule stated in the first two columns. Primary Exception 8 bits 10 bits 8 bits 10 bits Bit number 0123 4567 0123 4567 89 0123 4567 0123 4567 89 00ab cdef 0101 abcd ef 0001 abcd 1bac 0010 1d 01ab cdef a010 1bcd ef 0110 1010 0101 0101 00 10ab cdef ab01 01cd ef 1001 abcd ab00 cd01 01 11ab cdef abc0 101d ef 11a0 1bcd ab11 cd01 01 In general the 10 bit codes of the form 0101 01xx xx are reserved to perform channel control. Currently only two such codes are implemented. Idle indicates when no data is being transmitted. Start indicates the start of a packet. Currently a packet contains only one data byte. Additional codes: 0123 4567 89 Idle 0101 0101 01 Alternate Idle 1010 1010 10 Start 0101 0111 11 Of course none of this recoding matters with the current design. Only with long packet lengths and transmit/receive clock frequencies that are dramatically different will this recoding become important. Receive This block, in combination with a small amount of external circuitry, has three basic functions: synchronize the receive code to the receive data, recover clock and data from the receive data, and implement three SBus registers. Receive code synchronization is accomplished through a combination of two techniques. The first looks for rising edge transitions of the receive data which are too close together and declaring loss of lock each time too many such transitions occur quickly. To accomplish this the raw receive data coming in on RxData is synchronized and passed throught a filter which produces a one for each rising edge which appears as a clean 0011 sequence. This filter eliminates rising edges which are just one clock tick wide noise bursts. There is a six bit counter which measures the time from the last rising edge. This counter value is compared with a 6 bit register accessible from the SBus. If the counter value is smaller than the SBus register value then a pulse of length 5 CK cycles (1 microsecond) is emitted. This circuit is essentially a retriggerable one shot, so that if illegal transitions occur continuously then the ToInt output will be a constant one. Conversely, if no illegal transitions are detected, then ToInt will be a constant zero. CodeLock is the integration and threshold of ToInt. The integration is performed by a simple RC network with a time constant of approximately 50 microseconds. Thresholding is accomplished with a voltage comparator setup with a slight amount of hysterisis. Thus CodeLock is a signal which goes low when too many narrow transitions occur. The second code synchronization technique relies upon AmpLock, a signal produced by the receiver to eliminate false locking. Whenever both CodeLock and AmpLock are high, and then one of them goes low, the phase of the receive code generator is slipped by 180 degrees. There is an additional line, SlipEnb, which forces the code generator to never slip, but this line is always high during normal operation. When SlibEnb is deasserted, an oscilloscope probe on the integration node can be used to adjust the threshold of the voltage comparator. ShiftInBit This cell implements a standard serial-in, parallel-out, shift register with shift enable. It is CLBMapped to reduce the amount of work the placer has to do in order to come up with a good placement. SlipClock This cell takes a 20 MHz clock and produces 5 MHz and 10 MHz clocks. The 5 MHz clock, CK, is used to clock the vast majority of the flip-flops in the design. The 10 MHz clock, CodeCK, is only used to clock the receive code generator. The control line, Slip, causes the phase of CodeCK to slip by 180 degrees each time a rising edge occurs on it. While the receive code is locked to the transmit code, this control line is cycled frequently enough that the effective frequency of the receive code clock is the same as the transmit code clock frequency. Lock This cell recovers clock and data from the incoming signal. First, the signal is passed through a finite state machine (FSM) which filters out spurious pulses. The FSM has four states, 00, 01, 10, and 11, which correspond roughly to the number of ones seen in the last four cycles. State 00 causes the output SR flip-flop to reset and state 11 causes it to set. The signal can diddle around arbitrarily within the 01 and 10 states without affecting the output. Following the spurious pulse filter is a rising edge detector. The output of this detector is the pulse to which the phase locked loop synchronizes itself. The two flops in the middle record the existence of an early or late input pulse. The upper counter is the main state counter for the PLL. It counts from 0 to either 29, 30 or 31. It counts to 29 if the pulse is early, to 30 if the pulse is dead on, and 31 if the pulse is late. Thus the baud rate must be 30 times CK, which for a 200 nsec CK, is 6 microseconds. If both, or neither of, the early and late flip-flops are set then the loop does not adjust itself, i.e. it counts to 30. The lower counter acts as a data recovery filter. It counts the number of one bits sampled during any baud. If 16 or more ones are detected then the baud is declared a one, otherwise it is declared a zero. Note that this biases the circuit slightly towards declaring zeroes, since there are normally 31 samples, not 32. Assemble This block takes the serial data and clock and reassembles the data into a parallel byte. It uses a closed-loop, shift-register type controller with two states, Idle and Receive. Decode10to8 recognizes the start pattern which causes the state to change from Idle to Receive. After the counter has counted 10 bits into the shift register, the byte is transferred from the shift register into a buffer register. Data is clamped low while the receiver is out of lock to prevent random noise from triggering the assembly mechanism. RxStart is provided for testing as described in the ErrorGen documentation. ResetEnableCounter and ResetCounter These are standard synchronous counters with ripple carry. The main cell is CLBMapped to assist the placer. The proper expressions to cause the counter to be fully placed are included, but are currently commented out. Mux2, SR, RegBitD, CtlSynch, RegBit, MuxEnbFF These cells are miscellaneous bits and pieces which are so obvious I hardly think it worthwhile to say anything about them. ErrorGen This cell was included as a hack after the fact. When loopback testing is performed using both the local transmitter and local receiver this circuit will produce an error pulse if RxStart does not rise within ~8 CK cycles of TxStart rising. This makes it easy to trap errors which result from corrupted start patterns. It does not catch the case of corrupted data patterns. Physical Implementation A wire-wrap implementation of the controller currently exists. The schematic for a pcb version is in the cell PCB in the schematics. The details of each of these implementations are discussed in the sections below. Wirewrapped Implementation Currently two copies of the wire-wrap controller have been built. They can be distinguished by the little numbers 1 and 2 hand-written beween the +12 and -12 pins on the SBus connector. They are not identical and neither of them corresponds identically to the PCB cell in the schematics, although they both correspond in spirit. Both contain DACs that are wired to the Xilinx. These were put on the board when the integration was to be done digitally so that the integration value could be seen in the time domain on a silly scope. Some of the DAC input wires may be removed on one of the boards. Both contain PROM sockets, although neither is used. It is intended that the Xilinx boot program be loaded into one end of the PROM and the SBus Forth code loaded into the other end, although noone has yet figured out if that will actually work. Board 1 has an additional 393 circuit, with all the fixed and variable resistors that go with it. It is currently not used. Both boards have reset buttons connected to the Xilinx. This is necessary for loading them through XACT. PCB Implementation The PCB cell in the schematics describes the intended pcb implementation. The pcb version has never been built. The known errors include: one 1736 is not large enough to program a 3090; if J3 is left unjumpered the Xilinx expects to be loaded from the PC through J5, however there must also be a mechanism for asserting Reset* in this case. Simulation [DATools7.0]SpreadRadio.df contains several .mesa files, only one of which, RadioTest.mesa, is of any real interest anymore. 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