DIRECTORY BitOps, Core, Ports, Rosemary, RosemaryUser; RadioTest: CEDAR PROGRAM IMPORTS BitOps, Ports, Rosemary, RosemaryUser = BEGIN OPEN Ports; SSCtlPorts: TYPE = REF SSCtlPortsRec; SSCtlPortsRec: TYPE = RECORD[ nBR, nBG, nReset, nSel, nAS, SBusClk, nLErr, nAck0, nAck1, nAck2, Siz, Read, PA, Data, TxClock, TxCode, TxData, TxEnable, RxClock, RxCode, RxData, Lock, Sample, SampleData, Illegal, T0, SerialRegOut, Serial0: Port _ NIL]; Warning: SIGNAL = CODE; SSCtlTestProc: RosemaryUser.TestProc = { ports: SSCtlPorts _ SSCtlInitialize[p, cellType.public, Eval ! Rosemary.Stop => IF reason = $BoolWireHasX THEN RESUME ELSE REJECT]; {OPEN ports; txData: NAT = 0; txCtl: NAT = 1; rxData: NAT = 2; rxCtl: NAT = 3; serialCtl: NAT = 4; serialIntegrate: NAT = 0; serialDecay: NAT = 1; serialLockThreshold: NAT = 2; serialUnlockThreshold: NAT = 3; SBusStore: PROC [adr: NAT, value: NAT] = { PB[nSel, FALSE, force]; PB[nAS, FALSE, force]; PB[nLErr, TRUE, expect]; PB[nAck0, TRUE, expect]; PD[nAck1, inspect]; PB[nAck2, TRUE, expect]; PDW[Siz, 1, force]; PB[Read, FALSE, force]; PDW[PA, adr, force]; PDW[Data, BitOps.DShift[value, 24, 32], force]; THROUGH [1..255] DO CycleClock[ports, Eval]; IF NOT GB[nAck1] THEN EXIT; REPEAT FINISHED => SIGNAL Warning; ENDLOOP; PB[nAS, TRUE, force]; CycleClock[ports, Eval]; PB[nSel, TRUE, force]; CycleClock[ports, Eval]; }; SBusFetch: PROC [adr: NAT] RETURNS [value: NAT] = { PB[nSel, FALSE, force]; PB[nAS, FALSE, force]; PB[nLErr, TRUE, expect]; PB[nAck0, TRUE, expect]; PD[nAck1, inspect]; PB[nAck2, TRUE, expect]; PDW[Siz, 1, force]; PB[Read, TRUE, force]; PDW[PA, adr, force]; PD[Data, inspect]; THROUGH [1..255] DO CycleClock[ports, Eval]; IF NOT GB[nAck1] THEN EXIT; REPEAT FINISHED => SIGNAL Warning; ENDLOOP; value _ BitOps.ELFD[GDW[Data], 0, 8, 32]; PB[nAS, TRUE, force]; CycleClock[ports, Eval]; PB[nSel, TRUE, force]; CycleClock[ports, Eval]; }; serialBitCount: NAT = 12; SerialStore: PROC [value: NAT, reg: NAT] = { OPEN BitOps; serialCtlRegLen: NAT = 8; serialDoIt: NAT = 0; serialBitOfData: NAT = 1; serialRegAdr: NAT = 2; serialRegAdrLen: NAT = 2; serialBitAdr: NAT = 4; serialBitAdrLen: NAT = 4; d: BitWord _ BitWordZero; d _ ICIW[reg, d, serialRegAdr, serialRegAdrLen, serialCtlRegLen]; FOR bitIndex:NAT IN [0..serialBitCount) DO d _ IBIW[FALSE, d, serialDoIt, serialCtlRegLen]; d _ ICIW[bitIndex, d, serialBitAdr, serialBitAdrLen, serialCtlRegLen]; d _ IBIW[EBFW[value, serialBitCount-bitIndex-1, serialBitCount], d, serialBitOfData, serialCtlRegLen]; SBusStore[serialCtl, d]; d _ IBID[TRUE, d, serialDoIt, serialCtlRegLen]; SBusStore[serialCtl, d]; CycleClock[ports, Eval, 2*serialBitCount]; ENDLOOP; }; PD[TxEnable, inspect]; SBusStore[txCtl, 40H]; IF NOT GB[TxEnable] THEN SIGNAL Warning; PD[Serial0, inspect]; SerialStore[00AH, serialIntegrate]; IF GDW[Serial0]#00AH THEN SIGNAL Warning; SBusStore[rxCtl, 32H]; SerialStore[004H, serialLockThreshold]; SerialStore[006H, serialUnlockThreshold]; SerialStore[001H, serialDecay]; CycleClock[ports, Eval, 10*serialBitCount]; PB[Lock, TRUE, expect]; CycleClock[ports, Eval]; PD[Lock, none]; THROUGH [1..10] DO PB[TxData, FALSE, none]; CycleClock[ports, Eval, 16]; PB[TxData, TRUE, none]; CycleClock[ports, Eval, 16]; PB[TxData, FALSE, none]; CycleClock[ports, Eval, 16]; PB[TxData, TRUE, none]; CycleClock[ports, Eval, 16]; ENDLOOP; PB[Lock, FALSE, expect]; CycleClock[ports, Eval]; PD[Lock, none]; PD[TxData, inspect]; CycleClock[ports, Eval, 510]; -- initialize receiver IF BitOps.EBFD[SBusFetch[txCtl], 0, 8] THEN SIGNAL Warning; -- tx already busy? SBusStore[txData, 55H]; IF NOT BitOps.EBFD[SBusFetch[txCtl], 0, 8] THEN SIGNAL Warning; -- tx failed to go busy? THROUGH [1..100] DO IF BitOps.EBFD[SBusFetch[rxCtl], 0, 8] THEN EXIT; REPEAT FINISHED => SIGNAL Warning; -- rx failed to go ready? ENDLOOP; IF SBusFetch[rxData]#55H THEN SIGNAL Warning; -- incorrect data? }}; SSCtlInitialize: PROC [p: Ports.Port, public: Core.Wire, eval: RosemaryUser.TestEvalProc] RETURNS [ports: SSCtlPorts]= { ports _ NEW[SSCtlPortsRec]; {OPEN ports; [nBR, nBG, nReset, nSel, nAS, SBusClk, nLErr, nAck0, nAck1, nAck2] _ Ports.BindPorts[public, p, "nBR", "nBG", "nReset", "nSel", "nAS", "SBusClk", "nLErr", "nAck0", "nAck1", "nAck2"]; [Siz, Read, PA, Data, TxClock, TxCode, TxData, TxEnable, RxClock, RxCode, RxData] _ Ports.BindPorts[public, p, "Siz", "Read", "PA", "Data", "TxClock", "TxCode", "TxData", "TxEnable", "RxClock", "RxCode", "RxData"]; [Lock, Sample, SampleData, Illegal, T0, SerialRegOut, Serial0] _ Ports.BindPorts[public, p, "Lock", "Sample", "SampleData", "Illegal", "T0", "SerialRegOut", "Serial0"]; PB[nBR, TRUE, force]; PB[nBG, TRUE, force]; PB[nReset, TRUE, force]; PB[nSel, TRUE, force]; PB[nAS, TRUE, force]; PB[nLErr, TRUE, force]; PB[nAck0, TRUE, force]; PB[nAck1, TRUE, force]; PB[nAck2, TRUE, force]; PDW[Siz, 0, force]; PB[Read, TRUE, force]; PDW[PA, 0, force]; PDW[Data, 0, force]; PD[TxCode, none]; PD[TxData, none]; PD[TxEnable, none]; PD[RxCode, none]; PB[RxData, TRUE, force]; PD[Lock, none]; PD[Sample, none]; PD[SampleData, none]; PD[Illegal, none]; PD[T0, none]; PD[SerialRegOut, none]; PD[Serial0, none]; PB[TxClock, TRUE, force]; CycleClock[ports, eval]; }}; CycleClock: PROC [ports: SSCtlPorts, eval: RosemaryUser.TestEvalProc, count: NAT _ 1] = { OPEN ports; THROUGH [1..count] DO PB[RxData, GB[TxData], force]; PB[SBusClk, FALSE, force]; PB[TxClock, NOT GB[TxClock], force]; PB[RxClock, FALSE, force]; eval[clockEval: TRUE]; eval[clockEval: FALSE]; PB[RxData, GB[TxData], force]; PB[SBusClk, TRUE, force]; PB[RxClock, TRUE, force]; eval[clockEval: TRUE]; eval[clockEval: FALSE]; ENDLOOP; }; RosemaryUser.RegisterTestProc["SSCtl", SSCtlTestProc]; END. zRadioTest.mesa Copyright Σ 1987 by Xerox Corporation. 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