DIRECTORY  Core, Rosemary, RosemaryUser, Ports;RadioLock: CEDAR PROGRAMIMPORTS Rosemary, RosemaryUser, Ports = BEGIN OPEN Ports;RadioLockPorts: TYPE = REF RadioLockPortsRec;RadioLockPortsRec: TYPE = RECORD[CK, LegalCount, Legal, Illegal, Slip, SlipCount, Lock: Port _ NIL];RadioLockTestProc: RosemaryUser.TestProc = {ports: RadioLockPorts _ Initialize[p, cellType.public, Eval ! Rosemary.Stop => IF reason = $BoolWireHasX THEN RESUME ELSE REJECT];{OPEN ports;FOR slipCount: INT IN [0..4) DOPDW[SlipCount, slipCount, force];PB[Legal, TRUE, force];CycleClock[ports, Eval];THROUGH [1..2] DO CycleClock[ports, Eval]; ENDLOOP;PB[Legal, FALSE, force];PB[Illegal, TRUE, force];CycleClock[ports, Eval];PB[Illegal, FALSE, force];THROUGH [1..10] DO CycleClock[ports, Eval]; ENDLOOP;ENDLOOP;}};Initialize: PROC [p: Ports.Port, public: Core.Wire, eval: RosemaryUser.TestEvalProc] RETURNS [ports: RadioLockPorts]= {ports _ NEW[RadioLockPortsRec];{OPEN ports;[CK, LegalCount, Legal, Illegal, Slip, SlipCount, Lock] _ Ports.BindPorts[public, p, "CK", "LegalCount", "Legal", "Illegal", "Slip", "SlipCount", "Lock"];PDW[LegalCount, 1, force];PB[Legal, FALSE, force];PB[Illegal, FALSE, force];PB[Slip, FALSE, none];PDW[SlipCount, 0, force];PB[Lock, FALSE, none];CycleClock[ports, eval];}};CycleClock: PROC [ports: RadioLockPorts, eval: RosemaryUser.TestEvalProc] = {OPEN ports;PB[CK, FALSE, force];eval[clockEval: TRUE];eval[clockEval: FALSE];PB[CK, TRUE, force];eval[clockEval: TRUE];eval[clockEval: FALSE];};LegalCheckPorts: TYPE = REF LegalCheckPortsRec;LegalCheckPortsRec: TYPE = RECORD[Edge, CK, MinDelay, Legal, Illegal: Port _ NIL];LegalCheckTestProc: RosemaryUser.TestProc = {ports: LegalCheckPorts _ LegalCheckInitialize[p, cellType.public, Eval ! Rosemary.Stop => IF reason = $BoolWireHasX THEN RESUME ELSE REJECT];{OPEN ports;PDW[MinDelay, 7, force];THROUGH [1..2] DOPB[Edge, TRUE, force];LegalCheckCycleClock[ports, Eval];PB[Edge, FALSE, force];THROUGH [1..100] DO LegalCheckCycleClock[ports, Eval]; ENDLOOP;ENDLOOP;}};LegalCheckInitialize: PROC [p: Ports.Port, public: Core.Wire, eval: RosemaryUser.TestEvalProc] RETURNS [ports: LegalCheckPorts]= {ports _ NEW[LegalCheckPortsRec];{OPEN ports;[Edge, CK, MinDelay, Legal, Illegal] _ Ports.BindPorts[public, p, "Edge", "CK", "MinDelay", "Legal", "Illegal"];PB[Edge, FALSE, force];PDW[MinDelay, 0, force];PB[Legal, FALSE, none];PB[Illegal, FALSE, none];LegalCheckCycleClock[ports, eval];}};LegalCheckCycleClock: PROC [ports: LegalCheckPorts, eval: RosemaryUser.TestEvalProc] = {OPEN ports;PB[CK, FALSE, force];eval[clockEval: TRUE];eval[clockEval: FALSE];PB[CK, TRUE, force];eval[clockEval: TRUE];eval[clockEval: FALSE];};AssDisPorts: TYPE = REF AssDisPortsRec;AssDisPortsRec: TYPE = RECORD[ToReg, FromReg, ReadEnable, WriteEnable, IOCK, Address, TxData, RxData, Lock, CK: Port _ NIL];AssDisTestProc: RosemaryUser.TestProc = {ports: AssDisPorts _ AssDisInitialize[p, cellType.public, Eval ! Rosemary.Stop => IF reason = $BoolWireHasX THEN RESUME ELSE REJECT];{OPEN ports;PDW[Address, 4, force];PDW[ToReg, 85, force];PB[WriteEnable, TRUE, force];THROUGH [1..600] DOPB[RxData, GB[TxData], force];AssDisCycleClock[ports, Eval];ENDLOOP;}};AssDisInitialize: PROC [p: Ports.Port, public: Core.Wire, eval: RosemaryUser.TestEvalProc] RETURNS [ports: AssDisPorts]= {ports _ NEW[AssDisPortsRec];{OPEN ports;[ToReg, FromReg, ReadEnable, WriteEnable, IOCK, Address, TxData, RxData, Lock, CK] _ Ports.BindPorts[public, p, "ToReg", "FromReg", "ReadEnable", "WriteEnable", "IOCK", "Address", "TxData", "RxData", "Lock", "CK"];PDW[ToReg, 0, force];PDW[FromReg, 0, none];PB[ReadEnable, FALSE, force];PB[WriteEnable, FALSE, force];PDW[Address, 0, force];PB[TxData, FALSE, inspect];PB[RxData, FALSE, force];PB[Lock, TRUE, force];AssDisCycleClock[ports, eval];}};AssDisCycleClock: PROC [ports: AssDisPorts, eval: RosemaryUser.TestEvalProc] = {OPEN ports;PB[CK, FALSE, force];PB[IOCK, FALSE, force];eval[clockEval: TRUE];eval[clockEval: FALSE];PB[CK, TRUE, force];PB[IOCK, TRUE, force];eval[clockEval: TRUE];eval[clockEval: FALSE];};RosemaryUser.RegisterTestProc["RadioLock", RadioLockTestProc];RosemaryUser.RegisterTestProc["LegalCheck", LegalCheckTestProc];RosemaryUser.RegisterTestProc["AssDis", AssDisTestProc];END.   –  RadioLock.mesaCopyright س 1987 by Xerox Corporation.  All rights reserved.Barth, October 25, 1989 4:43:01 pm PDTRadioLockLegalCheckAssDis‌ت  –"cedar" styleک codeڑœ™K™<Kڑœ&™&K™ —ڑدk	œکKڑœ$ک$—Jک •StartOfExpansion[]ڑدn	œ‌œ‌کKڑ‌œ!ک(Kڑ‌œ‌œک—headڑœ	™	Kڑœ‌œ‌œک-ڑœ‌œ‌œک!Kڑœ>‌œکCKک —ڑ‍œک,KڑœO‌œ‌œ‌œ‌œ‌œک‚Kڑœ‌œکڑ‌œ‌œ‌œ‌کKڑ‌œک!Kڑ‌œ‌œ	کKڑœکKڑ‌œ‌œ‌œک3Kڑ‌œ‌œ	کKڑ‌œ
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