Introduction
This document is the theory of operation for the SBus board portion of the spread spectrum digital radio communications link. It assumes that the reader has the schematics available and directly references signal and cell names within them.
The majority of this document describes the design of the logic contained within the Xilinx field programmable gate array. Additional sections describe the physical implementation, both wirewrapped and pcb, simulation test suite, development software, and areas to investigate.
The SBus board has three basic functions: data handling, transmitter enable, and receive code synchronization. The data handling is complicated somewhat by the receive code synchronization which requires that 0101 sequences appear frequently in the received data stream. To accomplish this an 8-10 code is used so that such sequences appear with a guaranteed minimum frequency, independent of packet length.
There are three sources of time in the design, the sbus clock and the receive and transmit crystals. However, there are four synchronous timing domains in the design: sbus, main clock, receive code generation, and transmit code generation. The vast majority of the logic is run by the 5 MHz main clock, which is the 20 MHz receive clock divided by 4. The receive and transmit code generation clocks only clock the flip-flops in the respective code generators. The sbus clock only clocks the control path from nSel combined with nAS to Ack.
No simulation or timing analysis has been performed to guarantee that all of the combinatorial paths inside of the Xilinx will meet the setup times required by the flip-flops. However the clock is so slow for the vast majority of the logic that it seems extremely unlikely that this is a source of difficulty and, in any case, no problems which could be ascribed to timing failures have been noticed.
Cell Descriptions
Cell SSCtl is the top level schematic for the logic which is contained within the Xilinx. Cell PCB contains the board level schematics. The theory behind the small amount of circuitry contained on the PCB is covered in the Receive cell description.
Bits are numbered high order to low order in all cells except the PCB cell, where they are numbered low order to high order.
SSCtl
This cell forms the basic decomposition of the design between the bus interface, transmit logic, and receive logic. The ErrorGen cell was grafted on later to allow the capture of errors in which the transmitter sends a byte but the receiver fails to recognize the start pattern. This does not catch the other dominant failure mode, which is proper start pattern recognition followed by corrupted data. It would be fairly straightforward to further distort the division between transmit and receive so that this other failure mode is caught.
All of the public signals flowing into the SBusInterface are synchronous to the sbus clock. RegAdr is also synchronous to the sbus clock, although its setup and hold times relative to the other internal interface signals is so large and its usage is such that this distinction can safely be ignored. All of the remaining signals are synchronous to CK, except as noted below. The next section provides a functional pin description of the Xilinx. The SBus interface signals are not documented here. The reader should refer to the SBus Specification Rev A for their documentation.
Non SBus pins
TxClock (input) - nominally a 10 MHz clock. It actually must be slightly less than 10 MHz, e.g. 9.99981 MHz. Actual acceptable range for this clock has yet to be determined, see the Areas to Investigate section.
TxCode (output) - pseudorandom code used to spread the transmit signal. Synchronous with TxClock. For details look in the CodeGen cell description.
TxData (output) - transmit data. Note that this is synchronous with CK, which is divided down from the receive clock, not the transmit clock.
TxEnb (output) - transmit enable.
Error (output) - loopback error. Single pulse one CK period long each time transmit start is asserted without a matching receive start. For details look in the ErrorGen cell description.
ToInt (output) - to integrator. Single pulse one CK period long each time an invalid pair of transitions is detected.
RxCode (output) - pseudorandom code used to despread the received signal.
RxClock (input) - nominally a 20 MHz clock. It actually must be slightly more than 20 MHz, e.g. 20.00036 MHz. Actual acceptable range for this clock has yet to be determined, see the Areas to Investigate section.
RxData (input) - receive data. Synchronous with the RxClock of whichever transmitter has currently captured the receiver. Random noise if there is no such transmitter.
SlipEnb (input) - slip enable. When high this allows the clock generating the receive code to have half cycles deleted so that it can be synchronized with the transmit code of the current transmitter. When low no such synchronization can occur. This is useful when adjusting the integrator threshold.
CodeLock (input) - this is the output of the thresholded integration node.
AmpLock (input) - lock detection output from receiver.
SamClk (output) - phase lock loop clock.
SamData (output) - phase lock loop data.
SBusInterface
Mostly this block simply buffers the SBus data and address wires into the internal logic. It also provides the control signals necessary for byte reads and writes.
The control path is an open-ended shift register style sequencer. Each time a falling edge on nAS is detected while nSel is asserted a one is shifted into the beginning of the sequencer. This one is synchronized with CK and then, if the bus size is correct, asserts either RegRead or RegWrite for approximately one CK cycle. The trailing edge of this CK synchronous timing pulse is then synchronized back into the SBus clock timing domain and the proper acknowledgement is generated.
There is a shift register which has a constant one as its input. Its purpose is to ensure that the nAck wires are not asserted during the startup transient which occurs directly after programming the Xilinx.
It is extremely important that the delay from CK to nAck tristate enable be as short as possible. To accomplish this the tristate controls are mapped into a specific CLB and the path from them to the pad tristate enables are marked as critical. Another approach, not implemented here, is to bracket the time periods during which the nAck wire is transitioning with tristate enable and then merely toggling the data inputs of the tristate devices.
The combination of nBG and nReset is used to produce a known zero without using Gnd as the source. The tristate devices to which this known zero is tied must be present so that the Xilinx software won't assign these pads to some random flip-flop. Using Gnd as the known zero causes the Xilinx software to toss out the tristate devices as obviously useless.
AckFlop
This cell controls the tristate enables for acknowledgement. The A, B, and D inputs combine the bit shifting through the sequencer with the size information and startup transient suppression to enable the driver. The E input turns off the tristate enable two SBus clock cycles after enabling it.
Transmit
Both data and control are combined in this cell. The data path takes the byte presented by the buffered SBus data wires, combinatorially recodes it into 10 bits and then drops it into a shift register. The first bit of the the output shift register is broken out into discrete gates because otherwise the Xilinx software complains about the first SerialIn bit being set to a constant. The wires between the encoder and the shifter are reversed so that the bit pattern can be read off of an oscilloscope trace, left to right, most significant bit first.
The controller is a closed loop shift register style sequencer. After device programming all flip-flops are set to zero. One flip-flop in the sequencer is surrounded by inverters so that the initial zero appears as a one. This sequencer shifts at the bit rate, rather than at the basic CK rate, so all the flip-flops have enables which are asserted once per bit time. Writing a byte into the output shift register also causes a request for transmission to be posted in the transmit busy flip-flop. When a request is posted, and the idle pattern has been sent for at least 10 bits, and the last bit sent was a one, then the controller sends the start of packet sequence, which consists of 4 additional ones. After the controller has sent the start of packet sequence it transmits the 10 bits of the current byte and then returns to sending the idle pattern.
SBus register reads are implemented by chaining multiplexors rather than using tristate drivers. This block has a single register which can be read. The high order bit is the transmit busy bit. The next bit is the transmit enable bit. Only the transmit enable bit can be directly written.
ShiftOutBit
This cell implements a standard parallel load shift register with load and shift controls. It is CLBMaped in an effort to help the placement software find a good solution quickly.
CodeGen
This cell generates a pseudorandom sequence which is used for spreading and despreading the transmitted signal. It is a maximal length sequence for 6 bits, or 63. The illegal state, which is all zeroes, is detected and a one injected, to start the sequence generator.
Encode8to10 and Decode10to8
In order to guarantee that 0101 sequences occur sufficiently often to allow loss of lock to be detected the transmitted byte is recoded from 8 bits into 10 bits.
8 bits 0101 abcd ef
00ab cdef 0101 abcd ef
01ab cdef a010 1bcd ef
10ab cdef ab01 01cd ef
11ab cdef abc0 101d ef
0001 abcd 1abc 0010 1d
1001 abcd ab00 cd01 01
11a0 1bcd ab11 cd01 01
0101 01xx xx
Receive
ShiftInBit
SlipClock
Lock
Assemble
ResetEnableCounter and ResetCounter
Mux2, SR, RegBitD, CtlSynch, RegBit, MuxEnbFF
ErrorGen