<<>> Introduction This document is the theory of operation for the SBus board portion of the spread spectrum digital radio communications link. It assumes that the reader has the schematics available and directly references signal and cell names within them. The majority of this document describes the design of the logic contained within the Xilinx field programmable gate array. Additional sections describe the physical implementation, both wirewrapped and pcb, simulation test suite, development software, and areas to investigate. The SBus board has three basic functions: data handling, transmitter enable, and receive code synchronization. The data handling is complicated somewhat by the receive code synchronization which requires that 0101 sequences appear frequently in the received data stream. To accomplish this an 8-10 code is used so that such sequences appear with a guaranteed minimum frequency, independent of packet length. There are three sources of time in the design, the sbus clock and the receive and transmit crystals. However, there are four synchronous timing domains in the design: sbus, main clock, receive code generation, and transmit code generation. The vast majority of the logic is run by the 5 MHz main clock, which is the 20 MHz receive clock divided by 4. The receive code generation and transmit code generation clocks only clock the flip-flops in the respective code generators. The sbus clock only clocks the control path from nSel combined with nAS to Ack. No simulation or timing analysis has been performed to guarantee that all of the combinatorial paths inside of the Xilinx will meet the setup times required by the flip-flops. However the clock is so slow for the vast majority of the logic that it seems extremely unlikely that this is a source of difficulty and, in any case, no problems which could be ascribed to timing failures have been noticed. Cell Descriptions Cell SSCtl is the top level schematic for the logic which is contained within the Xilinx. Cell PCB contains the board level schematics. The theory behind the small amount of circuitry contained on the PCB is covered in the Receive cell description. Bits are numbered high order to low order in all cells except the PCB cell, where they are numbered low order to high order. SSCtl This cell forms the basic decomposition of the design between the bus interface, transmit logic, and receive logic. The ErrorGen cell was grafted on later to allow the capture of errors in which the transmitter sends a byte but the receiver fails to recognize the start pattern. This does not catch the other dominant failure mode, which is proper start pattern recognition followed by corrupted data. It would be fairly straightforward to further corrupt the division between transmit and receive so that this other failure mode is caught. All of the public signals flowing into the SBusInterface are synchronous to the sbus clock. RegAdr is also synchronous to the sbus clock, although its setup and hold times relative to the other internal interface signals is so large that this distinction can safely be ignored. All of the remaining signals are synchronous to CK, except as noted below. The next section provides a functional pin description of the Xilinx. The SBus interface signals are not documented here. The reader should refer to the SBus Specification Rev A for their documentation. Non SBus pins TxClock (input) - nominally a 10 MHz clock. It actually must be slightly less than 10 MHz, e.g. 9.99981 MHz. Actual acceptable range for this clock has yet to be determined, see the Areas to Investigate section. TxCode (output) - pseudorandom code used to spread the transmit signal. Synchronous with TxClock. For details look in the CodeGen cell description. TxData (output) - transmit data. Note that this is synchronous with CK, which is divided down from the receive clock, not the transmit clock. TxEnb (output) - transmit enable. Error (output) - loopback error. Single pulse one CK period long each time transmit start is asserted without a matching receive start. ToInt (output) - to integrator. Single pulse one CK period long each time an invalid pair of transitions is detected. RxCode (output) - pseudorandom code used to despread the received signal. RxClock (input) - nominally a 20 MHz clock. It actually must be slightly more than 20 MHz, e.g. 20.00036 MHz. Actual acceptable range for this clock has yet to be determined, see the Areas to Investigate section. RxData (input) - receive data. Synchronous with the RxClock of whichever transmitter has currently captured the receiver. Random noise if there is no such transmitter. SlipEnb (input) - slip enable. When high this allows the clock generating the receive code to have half cycles deleted so that it can be synchronized with the transmit code of the current transmitter. When low no such synchronization can occur. This is useful when adjusting the integrator threshold. CodeLock (input) - this is the output of the thresholded integration node. SBusInterface AckFlop Transmit ShiftOutBit CodeGen Encode8to10 and Decode10to8 Receive ShiftInBit SlipClock Lock Assemble ResetEnableCounter and ResetCounter Mux2, SR, RegBitD, CtlSynch, RegBit, MuxEnbFF ErrorGen Physical Implementation Wirewrapped Implementation Idiosyncrasies - DAC, PROM socket, additional 393 circuit on one, reset button PCB Implementation One 1736 not enough for 3090. Simulation <> <> <> <> <> Software <> <> <> <> <> <> <> <> <> <> Areas to Investigate Tx and Rx Clock Ranges Adaptive Locking Acquisition Time Reduction