<> <> <> <> <> <> <> <> DIRECTORY CD USING [Instance, InstanceList, Layer, Number, Object, Position, Rect, Transformation], CDProperties USING [PropList], RefTab USING [Ref], Rope USING [ROPE], SXQuadTree USING [QuadTreeRoot, RectDelta]; SX: CEDAR DEFINITIONS = BEGIN TranslateGeometry: PROCEDURE [cell: REF LogicalCell]; <> <> <> AddBox: PROCEDURE [ cir: REF Circuit, spinifexLayer: SpinifexLayerIndex, dim: CD.Rect, trans: CD.Transformation _ [], interestBloat: SXQuadTree.RectDelta _ [0,0,0,0], value: REF ANY _ NIL] RETURNS [cirNode: REF CircuitNode _ NIL]; <> AddRect: PROCEDURE [ cir: REF Circuit, lev: CD.Layer, dim: CD.Rect, trans: CD.Transformation _ [], value: REF CircuitNode _ NIL] RETURNS [cirNode: REF CircuitNode _ NIL]; IllegalConstruct: ERROR [rect: CD.Rect, reason: Rope.ROPE]; IllegalLayer: ERROR [rect: CD.Rect, lev: CD.Layer]; CreateLinkage: PROCEDURE [ cir: REF Circuit, source: CD.Instance, length, width: CD.Number] RETURNS [REF NodeLinkage]; <<--I do not yet understand whether source could be just an object>> LinkageAttach: PROCEDURE [link: REF NodeLinkage, attachType: ATOM, node: REF CircuitNode _ NIL]; NormalizeCircuit: PROCEDURE [cir: REF Circuit]; LookupNode: PROCEDURE [l: REF CircuitNode] RETURNS [REF CircuitNode]; FindRootNode: PROCEDURE [ -- look at HighlightNode for usage circuit: REF Circuit, subcircuitNode: REF CircuitNode, qualifier: LIST OF CD.Instance, insertIfNotInCircuit: BOOLEAN _ FALSE] RETURNS [ node: REF CircuitNode, rootQualifier: LIST OF CD.Instance]; MergeNode: PROCEDURE [circuit: REF Circuit, to, from: REF CircuitNode]; <> <> AdjustmentMode: TYPE = {relative, absolute}; AdjustNode: PROCEDURE [node: REF CircuitNode, layer: SpinifexLayerIndex, area: INT, perim: INT, mode: AdjustmentMode _ relative]; AnalysisState: TYPE = {notYetDone, useCircuit, reservedForFuture}; LogicalCell: TYPE = RECORD [ circuit: REF Circuit _ NIL, cellObj: CD.Object, -- bad circular ref... analysisState: AnalysisState _ notYetDone, rootOnInvocation: REF _ NIL, -- must do special check for root cells errorCount: INT _ 0, errorContext: Rope.ROPE _ NIL, -- Place where errors have been put if not in this cell. privateForSX: REF _ NIL]; -- for future use <> Circuit: TYPE = RECORD [ nodes: LIST OF REF CircuitNode _ NIL, linkages: LIST OF REF NodeLinkage _ NIL, linkageCount: RECORD [inSelf: INT _ 0, inChildren: INT _ 0], subcircuits: CD.InstanceList _ NIL, -- copies; have instance names mergeDirectory: RefTab.Ref _ NIL, -- establishes a correspondence between a node in this cell and a node in a cell at the end of a chain of cell instantations. Key: Circuit node (of a subcircuit); val: MergeRecList. properties: CDProperties.PropList _ NIL, invocationKey: INT, -- remove !! spinifexLayers: ARRAY SpinifexLayerIndex OF SXQuadTree.QuadTreeRoot]; -- build up on 1st step: translate CircuitNode: TYPE = RECORD [ superceded: REF CircuitNode _ NIL, -- NIL if analysis finished dim: LIST OF AreaPerimRec _ NIL, loc: NodeLocation, properties: CDProperties.PropList _ NIL]; NodeLocation: TYPE = RECORD [xy: CD.Position, layer: SpinifexLayerIndex]; AreaPerimRec: TYPE = RECORD [layer: SpinifexLayerIndex, area, perim: INT]; SignalName: TYPE = RECORD [ depth: INTEGER _ 0, name: Rope.ROPE, alias: REF SignalName _ NIL, makePort: BOOL _ FALSE]; -- in a root cell it will be considered to be a port <> maxConstraints: INTEGER = 16; ConstraintIndex: TYPE = [0..maxConstraints) _ ConstraintIndex.FIRST; spaceIndex: ConstraintIndex = 0; -- space regions. nodeIndex: ConstraintIndex = 1; -- node regions. excludeIndex: ConstraintIndex = 2; -- region excluded by Opaque cell. violateIndex: ConstraintIndex = 3; -- Opaque cell exclusion region violated techCIndexBase: ConstraintIndex = 4; -- Technology dependent clients should start number their constraints in each layer from here. Constraint: PUBLIC TYPE = RECORD [ -- belongs to the technology name: ATOM, index: ConstraintIndex, -- index into the constrain array hasCorrespondingNode: BOOLEAN _ FALSE, -- used where connectivity affects the rule and there is a corresponding layer which has the node associated with this region correspondingNodeLayer: SpinifexLayerIndex _ SpinifexLayerIndex.FIRST, -- way to attach node values to constraints by looking at other layers. specificCorrespondingNode: REF SX.CircuitNode _ NIL]; -- Specific node to which constraint is connected ConstraintPtr: TYPE = REF Constraint; ConstraintArray: TYPE = ARRAY ConstraintIndex OF ConstraintPtr _ ALL[NIL]; <> <> <> ConstraintResolution: TYPE = ARRAY ConstraintIndex OF ConstraintArray; NodeLinkage: TYPE = RECORD [ -- transistors source: CD.Instance, --could it be an object ? l, w: CD.Number, -- length, width nodes: LIST OF REF AttachedNode _ NIL]; AttachedNode: TYPE = RECORD [ attachmentType: ATOM, -- e.g. $Gate, $Drain, $Source node: REF CircuitNode]; MergeRecList: TYPE = LIST OF MergeRec; MergeRec: TYPE = RECORD [ applChain: LIST OF CD.Instance, -- bottom up, one application per subcircuit becomes: REF CircuitNode]; -- in the parent circuit ConversionProc: TYPE = PROCEDURE [ob: CD.Object, trans: CD.Transformation, cir: REF Circuit]; BoxMapProc: TYPE = PROCEDURE [cir: REF Circuit, dim: CD.Rect, trans: CD.Transformation, node: REF CircuitNode] RETURNS [cirNode: REF CircuitNode _ NIL]; maxSpinifexLayer: INTEGER = 8; SpinifexLayerIndex: TYPE = [0..maxSpinifexLayer); <> TechHandle: TYPE = RECORD [ numSpinifexLayers: SpinifexLayerIndex, -- Technology dependent (NMOS: 3, CMOS: 6). spinifexLayerNames: ARRAY SpinifexLayerIndex OF LayerNames, -- For Thyme layerInterestBloat: ARRAY SpinifexLayerIndex OF INTEGER _ ALL[0], -- (design number). Because bloat depends on material. These fields hold the maximum. rules: ARRAY SpinifexLayerIndex OF LIST OF REF GeometricRule _ ALL[NIL], constraintResolutions: ARRAY SpinifexLayerIndex OF REF ConstraintResolution _ ALL [NIL], cdLayerMapping: ARRAY CD.Layer OF LIST OF MapRec _ ALL[NIL], -- Map from ChipNDale rectangles to quad-tree rectangles. A ChipNDale rectangle may map (in TranslateGeometry) to several spinifex layers, as a conductive region on one, and as contraints on other conductive regions on other spinifex layers. illegalLayer: ARRAY CD.Layer OF BOOLEAN _ ALL[TRUE], -- To detect isolated curts that should only be used inside objects. combineNodeProperties: CombineNodePropertyProc _ NIL, -- For technology dependent properties. For merging phase. cellPostProcess: CellPostProcessProc _ NIL -- For technology dependent manipulation and checking. (e.g. cmos n-well connects) ]; CombineNodePropertyProc: TYPE = PROCEDURE [circuit: REF Circuit, to, from: CDProperties.PropList, fromNesting: LIST OF CD.Instance] RETURNS [CDProperties.PropList]; <> CellPostProcessProc: TYPE = PROCEDURE [cell: REF LogicalCell]; LayerNames: TYPE = RECORD [layerId: ATOM _ NIL, thymeName: Rope.ROPE _ NIL]; MapRec: TYPE = RECORD [ spinifexLayer: SpinifexLayerIndex, bloatFactor: INTEGER, value: REF ANY _ NIL]; <> < A new the region represents conductive material on this layer and a new node is created.>> < region represents a constraint on other material in this layer.>> < A procedural escape for more complex rectangle mapping. (e.g. for mapping n-well)>> <> GeometricRule: TYPE = RECORD [ extent: INTEGER, message: Rope.ROPE _ NIL, okIfConnected: BOOLEAN _ FALSE, trigger1, trigger2: PACKED ARRAY ConstraintIndex OF BOOLEAN _ ALL [FALSE]]; END. <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<>>