CMosRules.tioga
Written by: Mark Shand, September 7, 1984 2:34:06 pm PDT
Last Edited by: Shand, September 7, 1984 2:34:26 pm PDT
gbb March 25, 1986 4:18:18 pm PST
What follows is an informal description of the design rules for CMos-B implemented by the current version of Spinifex. To the best of my knowledge it is correct however be forewarned that the truth is in the code (see SXMaintenance) not in this message. Note: each cell in the hierarchy must satisfy these rules in isolation.
The rules:
Any material appearing on the cut, cut2, ovg & bur is flagged as an error if it appears in isolation (i.e. outside of a ChipNDale object like a Poly-metal contact).
Metal-2
4l Spacing between unconnected Metal-2
4l Width for any Metal-2
No rules are enforced regarding to the placement of Metal to Metal-2 contacts
Metal
3l Spacing between unconnected Metal
3l Width for any Metal
Polysilicon
2ýl Spacing between unconnected Polysilicon
2l Width for any Polysilicon
1l Spacing between Polysilicon and unconnected Diffusion of any flavour (including well contacts)
Polysilicon may abut Connected Diffusion of any flavour, but may not overlap it.
1ýl Spacing between Transistor Gate and Buried contact window.
Diffusion of any flavour (ndif, pdif, n-wCnt & p-wCnt)
3ýl Spacing between unconnected Diffusions
2l Width for any region of n-type or p-type Diffusion
n-type Diffusion
May not overlap p-type Diffusion (regardless of connectivity)
5l Spacing to well boundary
Well contact Diffusions
May appear in both the well and the substrate and may overlap the corresponding wiring diffusion (i.e. n-wCnt <=> ndif, p-wCnt <=> pdif)
n-Well
10l Spacing between wells
12l Width for any well
Wells must be connected to one and only one node through material on the n-wCnt layer touching the well (In fact a minimum overlap should be enforced but it is not)
The design rule regard isolated regions of n-wCnt as separate nodes, this may generate spurious errors for guard rings which are broken by polysilicon wires which cross the well boundary