<> <> <> <> <<>> DIRECTORY Core, CoreFlat, RefTab, IO, Rope, SymTab; SpiceOps: CEDAR DEFINITIONS = BEGIN <> FlatWire: TYPE = CoreFlat.FlatWire; ROPE: TYPE = Rope.ROPE; ConvData: TYPE = REF ConvDataRec; ConvDataRec: TYPE = RECORD[ rootCell: Core.CellType, outS, inS: IO.STREAM, wTable: RefTab.Ref, invTable: SymTab.Ref, nextId: CARD _ 0, initList: ROPE, tranList: ROPE, analysis: ROPE, printList: ROPE, optList: ROPE, modelsUsed: SymTab.Ref, temp: REAL _ 27.0, limpts: INT ]; <> gndName: ROPE; vddName: ROPE; pModel: ROPE; nModel: ROPE; diodeModel: ROPE; temp: REAL; modelTable: SymTab.Ref; <> spiceModel, -- $SpiceOpsModel <> spiceOptions, -- $SpiceOpsOptions <> analysisType, -- $SpiceOpsAnalysis <> spiceExtraLine: ATOM; -- $SpiceOpsExtraLine <> <> <> ReadModels: PROC [file: IO.STREAM]; <> <> <> CreateConvData: PROC [inputStream, outputStream: IO.STREAM] RETURNS [convData: ConvData]; WriteSpiceDeck: PROC [cellType: Core.CellType, convData: ConvData]; <<>> <> InitSpiceDeck: PROC [cellType: Core.CellType, convData: ConvData]; CloseSpiceDeck: PROC [convData: ConvData]; <> DisplaySpiceListing: PROC [convData: ConvData]; <> Comment: PROC [convData: ConvData, comment: ROPE]; Resistor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, tc1, tc2: REAL _ 0.0]; Capacitor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, incond: REAL _ 0.0]; Inductor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, incond: REAL _ 0.0]; CoupledInductors: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, l1, l2: REAL, k: REAL]; LosslessLine: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, z0: REAL, td: REAL]; Vccs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL]; Vcvs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL]; Cccs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL]; Ccvs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL]; Diode: PROC [convData: ConvData, n1, n2: FlatWire, model: ROPE, area: REAL]; BJT: PROC [convData: ConvData, c, b, e: FlatWire, model: ROPE, area: REAL]; MOSFet: PROC [convData: ConvData, gate, drain, source, bulk: FlatWire, model: ROPE, l, w: REAL]; VSource: PROC [convData: ConvData, n1, n2: FlatWire, dc: REAL _ 0.0]; ISource: PROC [convData: ConvData, n1, n2: FlatWire, ma: REAL _ 0.0]; PulseVS: PROC [convData: ConvData, n1, n2: FlatWire, v1, v2, td, tr, tf, pw, per: REAL _ 0.0]; SineGen: PUBLIC PROC [convData: ConvData, n1, n2: FlatWire, v0, vA, freq, td, theta: REAL _ 0.0]; ACSource: PUBLIC PROC [convData: ConvData, n1, n2: FlatWire, mag, phase: REAL _ 0.0]; Model: PUBLIC PROC [convData: ConvData, mName: ROPE]; <> END.