[_CD4_]<datools7.0>SpiceOps>SpiceOps.mesa!3

SpiceOps.mesa

written by Ch. Le Cocq March 2, 1987 4:12:28 pm PST

Christian Le Cocq April 7, 1988 6:21:06 pm PDT

DIRECTORY

Core,

CoreFlat,

RefTab,

IO,

Rope,

SymTab;

SpiceOps: CEDAR DEFINITIONS = BEGIN

Types

FlatWire: TYPE = CoreFlat.FlatWire;

ROPE: TYPE = Rope.ROPE;

ConvData: TYPE = REF ConvDataRec;

ConvDataRec: TYPE = RECORD[

rootCell: Core.CellType,

outS, inS: IO.STREAM,

wTable: RefTab.Ref,

invTable: SymTab.Ref,

nextId: CARD ← 0,

initList: ROPE,

tranList: ROPE,

analysis: ROPE,

printList: ROPE,

optList: ROPE,

modelsUsed: SymTab.Ref,

temp: REAL ← 27.0,

limpts: INT

];

Default names and values

gndName: ROPE;

vddName: ROPE;

pModel: ROPE;

nModel: ROPE;

diodeModel: ROPE;

temp: REAL;

modelTable: SymTab.Ref;

Optional specifications

spiceModel, -- $SpiceOpsModel

points to a ROPE which is used for the model field of the line corresponding to the cell.

spiceOptions, -- $SpiceOpsOptions

points to a ROPE which is concatenated with the .OPT line content.

analysisType, -- $SpiceOpsAnalysis

points to a ROPE which is a Spice analysis type i.e. "AC", "DC"... defaulted to "TRAN"

spiceExtraLine: ATOM; -- $SpiceOpsExtraLine

points to a ROPE which is inserted as a separate line in the file.

Loading of models

in SpiceInputGenImpl.mesa :

ReadModels: PROC [file: IO.STREAM];

The format is the same as for Spice. Lines which first word is not ".MODEL", "+" (Spice continuation) or "*" (Spice comment) raise a signal. If a given model is multiply defined, the last definition wins.

Translation to and from Spice format

in SpiceInputGenImpl.mesa :

CreateConvData: PROC [inputStream, outputStream: IO.STREAM] RETURNS [convData: ConvData];

WriteSpiceDeck: PROC [cellType: Core.CellType, convData: ConvData];

two lower level ones to use in case one wants to generate a spice deck from custom data:

InitSpiceDeck: PROC [cellType: Core.CellType, convData: ConvData];

CloseSpiceDeck: PROC [convData: ConvData];

in SpiceOutputViewImpl.mesa :

DisplaySpiceListing: PROC [convData: ConvData];

Elements to Spice input line procs

Comment: PROC [convData: ConvData, comment: ROPE];

Resistor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, tc1, tc2: REAL ← 0.0];

Capacitor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, incond: REAL ← 0.0];

Inductor: PROC [convData: ConvData, n1, n2: FlatWire, value: REAL, incond: REAL ← 0.0];

CoupledInductors: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, l1, l2: REAL, k: REAL];

LosslessLine: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, z0: REAL, td: REAL];

Vccs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];

Vcvs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];

Cccs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];

Ccvs: PROC [convData: ConvData, n0, n1, n2, n3: FlatWire, value: REAL];

Diode: PROC [convData: ConvData, n1, n2: FlatWire, model: ROPE, area: REAL];

BJT: PROC [convData: ConvData, c, b, e: FlatWire, model: ROPE, area: REAL];

MOSFet: PROC [convData: ConvData, gate, drain, source, bulk: FlatWire, model: ROPE, l, w: REAL];

VSource: PROC [convData: ConvData, n1, n2: FlatWire, dc: REAL ← 0.0];

ISource: PROC [convData: ConvData, n1, n2: FlatWire, ma: REAL ← 0.0];

PulseVS: PROC [convData: ConvData, n1, n2: FlatWire, v1, v2, td, tr, tf, pw, per: REAL ← 0.0];

SineGen: PUBLIC PROC [convData: ConvData, n1, n2: FlatWire, v0, vA, freq, td, theta: REAL ← 0.0];

ACSource: PUBLIC PROC [convData: ConvData, n1, n2: FlatWire, mag, phase: REAL ← 0.0];

Model: PUBLIC PROC [convData: ConvData, mName: ROPE];

only for models registred with SpiceOps.

END.