C0 W0 23 0 W1 0 1 A0 CoreName r R0 "Vdd" W2 0 1 A0 r R1 "RtH" W3 0 1 A0 r R2 "AddVb" W4 0 1 A0 r R3 "LoadMxE" W5 0 2 A0 r R4 "X" A1 GivenName a A1 W6 0 1 A0 r R5 "LoadDnE" W7 0 1 A0 r R6 "Ck" W8 0 1 A0 r R7 "nVDr" W9 0 1 A0 r R8 "VDr" WA 0 1 A0 r R9 "GetNZR" WB 0 1 A0 r RA "CVDr" WC 0 1 A0 r RB "RegVb" WD 0 1 A0 r RC "LtV" WE 0 1 A0 r RD "Invert" WF 0 1 A0 r RE "FndNZR" W10 0 1 A0 r RF "Clock" W11 0 1 A0 r R10 "nCk" W12 0 1 A0 r R11 "RegPd" W13 0 1 A0 r R12 "RtV" W14 0 1 A0 r R13 "ShiftBuffer" W15 0 1 A0 r R14 "nCVDr" W16 0 1 A0 r R15 "LtH" W17 0 1 A0 r R16 "Gnd" 3 A0 r R17 "MultControlSC" A2 numRows i 8 A3 Layout a A4 SCRemote R18 "Record" 12 W18 24 0 W1 WB W5 WD W16 W10 W7 W14 W2 W19 0 0 W11 W15 W1A 0 0 W3 W12 W1B 0 0 W9 WA W1C 0 0 W1D 4 2 A0 r R19 "I" A1 a A1 W6 W4 WF WE WC W13 W8 W17 W1E 4 0 W1 W14 W5 W17 0 C1 W0 4 0 W1 0 2 A0 r R0 A5 PortData l agg n 0 W2 0 2 A0 r R1A "I" A5 l agg n 0 W3 0 2 A0 r R4 A5 l agg d 0 W4 0 2 A0 r R16 A5 l agg n 0 4 A0 r R1B "driver" A6 RoseBehave r R1C "LogicDriver" A7 CoreCutLabel lor 1 R1D "LogicMacro" A8 LogForStats r R1E "Driver d=300" R18 2 W5 5 0 W1 W3 W2 W6 0 0 W4 W7 4 0 W1 W6 W3 W4 0 C2 W0 4 0 W1 0 2 A0 r R1F "Vdd" A5 l agg n 0 W2 0 2 A0 r R20 "I" A5 l agg n 0 W3 0 2 A0 r R21 "X" A5 l agg d 0 W4 0 2 A0 r R22 "Gnd" A5 l agg n 0 4 A0 r R23 "Buffer" A6 r R24 "LogicInv" A7 lor 1 R25 "Logic" A8 r R26 "Buffer d=75" R27 "Sequence" C3 W0 4 0 W1 0 3 A0 r R1F A9 RoseFixedWire H A5 l agg n 0 W2 0 3 A0 r R20 AA PortTesterDrive b agg f 0 A5 l agg n 0 W3 0 4 A0 r R21 AA b agg e 0 A5 l agg d 0 AB Output r R28 "~I" W4 0 3 A0 r R22 A9 L A5 l agg n 0 9 AC LichenTransistorTolerances r R29 "0.8, 0.8" A0 r R2A "invBuffer" A7 lor 2 R2B "LogicMacro" R2C "Logic" AD CellArea i 159744 A3 a AE GetLibrary A6 r R2D "Combinatorial" AF Combinatorial rb 1 A10 Library r R2E "SCLibCMOSBMask" A8 r R2F "InvB" R18 2 W5 4 0 W1 W3 W2 W4 W6 4 0 W2 W1 W3 W1 0 C4 W0 4 0 W1 0 1 A0 r R30 "gate" W2 0 1 A0 r R31 "ch1" W3 0 1 A0 r R32 "ch2" W4 0 1 A0 r R1F 2 A11 CoreTransistorWidth i 100 A12 CoreTransistorLength i 2 R33 "Transistor" pE W7 3 0 W2 W3 W4 0 C5 W0 3 0 W1 0 1 A0 r R30 W2 0 1 A0 r R31 W3 0 1 A0 r R32 2 A11 i 48 A12 i 2 R33 nE 38 -1 -1 W8 4 0 W1 W2 W6 W4 0 C6 W0 4 0 W1 0 2 A0 r R1F A5 l agg n 0 W2 0 2 A0 r R20 A5 l agg n 0 W3 0 2 A0 r R21 A5 l agg d 0 W4 0 2 A0 r R22 A5 l agg n 0 4 A0 r R23 A6 r R24 A7 lor 1 R25 A8 r R34 "Buffer d=9" R27 C3 5 -1 -1 W1F 5 0 W1 W10 W11 W7 W17 0 C7 W0 5 0 W1 0 2 A0 r R0 A5 l agg n 0 W2 0 2 A0 r R1A A5 l agg n 0 W3 0 2 A0 r R35 "nX" A5 l agg d 0 W4 0 2 A0 r R4 A5 l agg d 0 W5 0 2 A0 r R16 A5 l agg n 0 4 A0 r R36 "symDriver" A6 r R37 "LogicSymDriver" A7 lor 1 R1D A8 r R38 "SymDriver d=370" R18 2 W6 5 0 W1 W4 W3 W2 W5 W7 4 0 W1 W4 W3 W5 0 C8 W0 4 0 W1 0 2 A0 r R1F A5 l agg n 0 W2 0 2 A0 r R20 A5 l agg n 0 W3 0 2 A0 r R21 A5 l agg d 0 W4 0 2 A0 r R22 A5 l agg n 0 4 A0 r R23 A6 r R24 A7 lor 1 R25 A8 r R39 "Buffer d=93" R27 C3 47 -1 -1 W8 4 0 W1 W2 W4 W5 0 C9 W0 4 0 W1 0 2 A0 r R0 A5 l agg n 0 W2 0 2 A0 r R1A A5 l agg n 0 W3 0 2 A0 r R4 A5 l agg d 0 W4 0 2 A0 r R16 A5 l agg n 0 4 A0 r R3A "driver" A6 r R1C A7 lor 1 R1D A8 r R3B "Driver d=463" R18 2 W5 5 0 W1 W6 0 0 W3 W2 W4 W7 4 0 W1 W6 W3 W4 0 CA W0 4 0 W1 0 2 A0 r R1F A5 l agg n 0 W2 0 2 A0 r R20 A5 l agg n 0 W3 0 2 A0 r R21 A5 l agg d 0 W4 0 2 A0 r R22 A5 l agg n 0 4 A0 r R23 A6 r R24 A7 lor 1 R25 A8 r R3C "Buffer d=116" R27 C3 58 -1 -1 W8 4 0 W1 W2 W6 W4 0 CB W0 4 0 W1 0 2 A0 r R1F A5 l agg n 0 W2 0 2 A0 r R20 A5 l agg n 0 W3 0 2 A0 r R21 A5 l agg d 0 W4 0 2 A0 r R22 A5 l agg n 0 4 A0 r R23 A6 r R24 A7 lor 1 R25 A8 r R3D "Buffer d=11" R27 C3 6 -1 -1 W20 5 0 W1 WE WD W16 W17 0 CC W0 5 0 W1 0 1 A0 r R0 W2 0 1 A0 r R3E "In" W3 0 1 A0 r R3F "nOut" W4 0 1 A0 r R40 "Out" W5 0 1 A0 r R16 1 A0 r R41 "MuxDualDr" R18 2 W6 5 0 W1 W4 W3 W2 W5 W7 4 0 W1 W4 W3 W5 0 CD W0 4 0 W1 0 1 A0 r R0 W2 0 2 A0 r R21 A1 a A1 W3 0 2 A0 r R20 A1 a A1 W4 0 1 A0 r R16 1 A0 r R42 "MuxInvDr" R18 2 W5 4 0 W1 W3 W2 W4 W6 4 0 W1 W3 W2 W4 0 C3 W7 4 0 W1 W3 W2 W4 0 C3 W8 4 0 W1 W3 W2 W5 0 CD W21 4 0 W1 WA W19 W17 0 CE W0 4 0 W1 0 3 A0 r R1F A9 H A5 l agg n 0 W2 0 3 A0 r R20 AA b agg f 0 A5 l agg n 0 W3 0 4 A0 r R21 AA b agg e 0 A5 l agg d 0 AB r R28 W4 0 3 A0 r R22 A9 L A5 l agg n 0 9 AC r R29 A0 r R43 "inv" A7 lor 2 R2B R2C AD i 106496 A3 a AE A6 r R2D AF rb 1 A10 r R2E A8 r R44 "Inv" R18 2 W5 4 0 W1 W2 W3 W4 W6 4 0 W2 W3 W1 W1 0 CF W0 4 0 W1 0 2 A0 r R30 A1 a A1 W2 0 2 A0 r R32 A1 a A1 W3 0 2 A0 r R31 A1 a A1 W4 0 2 A0 r R1F A1 a A1 1 A0 r R45 "p50" R18 1 W5 4 0 W1 W2 W3 W4 W6 4 0 W1 W3 W2 W4 0 C10 W0 4 0 W1 0 1 A0 r R30 W2 0 1 A0 r R31 W3 0 1 A0 r R32 W4 0 1 A0 r R1F 2 A11 i 50 A12 i 2 R33 pE W7 3 0 W4 W2 W3 0 C11 W0 3 0 W1 0 2 A0 r R32 A1 a A1 W2 0 2 A0 r R30 A1 a A1 W3 0 2 A0 r R31 A1 a A1 1 A0 r R46 "n24" R18 1 W4 3 0 W3 W2 W1 W5 3 0 W2 W3 W1 0 C12 W0 3 0 W1 0 1 A0 r R30 W2 0 1 A0 r R31 W3 0 1 A0 r R32 2 A11 i 24 A12 i 2 R33 nE W22 5 0 W1 WA W13 W2 W17 0 CC W23 6 0 W1 WA W1C W4 WE W17 0 C13 W0 6 0 W1 0 2 A1 a A1 A0 r R0 W2 0 1 A0 r R47 "I-B" W3 0 1 A0 r R48 "X" W4 0 1 A0 r R49 "I-C" W5 0 1 A0 r R4A "I-A" W6 0 2 A1 a A1 A0 r R16 1 A0 r R4B "nor3" R18 1 W7 4 0 W1 W3 W8 3 2 A0 r R19 A1 a A1 W5 W2 W4 W6 W9 4 0 W1 W6 W8 W3 0 C14 W0 4 0 W1 0 1 A0 r R4C "Vdd" W2 0 1 A0 r R4D "Gnd" W3 3 1 A0 r R19 W4 0 0 W5 0 0 W6 0 0 W7 0 1 A0 r R4E "X" 2 A0 r R4F "Nor3" A8 r R50 "Nor n=3" R18 1 W0 W8 6 0 W1 W5 W7 W4 W6 W2 0 C15 W0 6 0 W1 0 3 A0 r R1F A9 H A5 l agg n 0 W2 0 3 A0 r R51 "I-B" AA b agg f 0 A5 l agg n 0 W3 0 4 A0 r R21 AA b agg e 0 A5 l agg d 0 AB r R52 "~(I-A + I-B + I-C)" W4 0 3 A0 r R53 "I-A" AA b agg f 0 A5 l agg n 0 W5 0 3 A0 r R54 "I-C" AA b agg f 0 A5 l agg n 0 W6 0 3 A0 r R22 A9 L A5 l agg n 0 8 AC r R29 A7 lor 2 R2B R2C AD i 212992 A3 a AE A6 r R2D AF rb 1 A0 r R55 "nor3" A10 r R2E R18 6 W7 8 0 W1 W2 W3 W4 W5 W8 0 0 W9 0 0 W6 WA 4 0 W4 W8 W1 W1 0 CF WB 4 0 W2 W9 W8 W1 0 CF WC 4 0 W5 W3 W9 W1 0 CF WD 3 0 W6 W5 W3 0 C11 WE 3 0 W6 W2 W3 0 C11 WF 3 0 W6 W4 W3 0 C11 W24 4 0 W1 W3 W19 W17 0 CD W25 5 0 W1 W1C W12 WC W17 0 CC W26 5 0 W1 W1A WE WF W17 0 C16 W0 5 0 W1 0 2 A1 a A1 A0 r R0 W2 0 1 A0 r R48 W3 0 1 A0 r R4A W4 0 1 A0 r R47 W5 0 2 A1 a A1 A0 r R16 1 A0 r R56 "nor2" R18 1 W6 4 0 W1 W2 W7 2 2 A0 r R19 A1 a A1 W3 W4 W5 W8 4 0 W1 W5 W7 W2 0 C17 W0 4 0 W1 0 1 A0 r R57 "Vdd" W2 0 1 A0 r R58 "Gnd" W3 2 1 A0 r R19 W4 0 0 W5 0 0 W6 0 1 A0 r R59 "X" 2 A0 r R5A "Nor2" A8 r R5B "Nor n=2" R18 1 W0 W7 5 0 W1 W5 W6 W4 W2 0 C18 W0 5 0 W1 0 3 A0 r R1F A9 H A5 l agg n 0 W2 0 3 A0 r R51 AA b agg f 0 A5 l agg n 0 W3 0 4 A0 r R21 AA b agg e 0 A5 l agg d 0 AB r R5C "~(I-A + I-B)" W4 0 3 A0 r R53 AA b agg f 0 A5 l agg n 0 W5 0 3 A0 r R22 A9 L A5 l agg n 0 8 AC r R29 A7 lor 2 R2B R2C AD i 159744 A3 a AE A6 r R2D AF rb 1 A0 r R5D "nor2" A10 r R2E R18 4 W6 6 0 W1 W3 W4 W2 W7 0 0 W5 W8 4 0 W4 W7 W1 W1 0 CF W9 3 0 W5 W2 W3 0 C11 WA 4 0 W2 W3 W7 W1 0 CF WB 3 0 W5 W4 W3 0 C11 W27 5 0 W1 WB W15 W1A W17 0 C19 W0 5 0 W1 0 2 A0 r R0 A5 l agg n 0 W2 0 2 A0 r R35 A5 l agg d 0 W3 0 2 A0 r R4 A5 l agg d 0 W4 0 2 A0 r R1A A5 l agg n 0 W5 0 2 A0 r R16 A5 l agg n 0 4 A0 r R5E "symDriver3" A8 r R5F "SymDriver d=2" A7 lor 3 R1D R1D R1D A6 r R37 R18 2 W6 5 0 W1 W4 W2 W3 W5 W7 4 0 W1 W2 W3 W5 0 CE W8 4 0 W1 W4 W2 W5 0 CE W28 4 0 W1 W17 W1D W1B 0 C1A W0 4 0 W1 0 1 A0 r R60 "Vdd" W2 0 1 A0 r R61 "Gnd" W3 4 1 A0 r R19 W4 0 0 W5 0 0 W6 0 0 W7 0 0 W8 0 1 A0 r R62 "X" 2 A0 r R63 "Or4" A8 r R64 "Or n=4" R18 1 W0 W9 7 0 W1 W7 W6 W8 W4 W5 W2 0 C1B W0 7 0 W1 0 3 A0 r R1F A9 H A5 l agg n 0 W2 0 3 A0 r R65 "I-D" AA b agg f 0 A5 l agg n 0 W3 0 3 A0 r R54 AA b agg f 0 A5 l agg n 0 W4 0 4 A0 r R21 AA b agg e 0 A5 l agg d 0 AB r R66 "I-A + I-B + I-C + I-D" W5 0 3 A0 r R53 AA b agg f 0 A5 l agg n 0 W6 0 3 A0 r R51 AA b agg f 0 A5 l agg n 0 W7 0 3 A0 r R22 A9 L A5 l agg n 0 8 AC r R29 A7 lor 2 R2B R2C AD i 319488 A3 a AE A6 r R2D AF rb 1 A0 r R67 "or4" A10 r R2E R18 9 W8 11 0 W1 W3 W9 0 0 WA 0 0 W2 W4 WB 0 0 W6 WC 0 0 W5 W7 WD 4 0 W5 W9 W1 W1 0 CF WE 4 0 W6 WB W9 W1 0 CF WF 4 0 W3 WA WB W1 0 CF W10 4 0 W1 WC W4 W7 0 C1C W0 4 0 W1 0 1 A0 r R1F W2 0 1 A0 r R20 W3 0 1 A0 r R21 W4 0 1 A0 r R22 1 A0 r R68 "inv24" R18 2 W5 4 0 W1 W3 W2 W4 W6 4 0 W2 W3 W1 W1 0 CF W7 3 0 W4 W2 W3 0 C11 W11 4 0 W2 WC WA W1 0 CF W12 3 0 W7 W2 WC 0 C11 W13 3 0 W7 W3 WC 0 C11 W14 3 0 W7 W6 WC 0 C11 W15 3 0 W7 W5 WC 0 C11 W29 5 0 W1 W8 W9 W1B W17 0 C1D W0 5 0 W1 0 1 A0 r R0 W2 0 1 A0 r R3F W3 0 1 A0 r R40 W4 0 1 A0 r R3E W5 0 1 A0 r R16 1 A0 r R69 "VbDr" R18 2 W6 5 0 W1 W2 W3 W4 W5 W7 4 0 W1 W5 W3 W2 0 C1E W0 4 0 W1 0 1 A0 r R1F W2 0 1 A0 r R22 W3 0 1 A0 r R21 W4 0 1 A0 r R20 1 A0 r R6A "InvBSeq" R18 3 W5 7 0 W1 W2 W3 W4 W6 4 0 W1 W4 W3 W2 W7 4 0 W1 W4 W3 W2 W8 4 0 W1 W4 W3 W2 W6 1 A0 r R6B "invBuffer0" C3 W7 1 A0 r R6C "invBuffer1" C3 W8 1 A0 r R6D "invBuffer2" C3 W8 4 0 W1 W5 W2 W4 0 C1E