SoftHdwSimulateImpl.mesa
Copyright Ó 1988 by Xerox Corporation. All rights reserved.
Barth, September 6, 1989 2:19:30 pm PDT
DIRECTORY BitOps, CD, CDProperties, CDSequencer, CDSequencerExtras, IO, Rope, SoftHdwAssembly, SoftHdwBasics, SoftHdwSimulate, TerminalIO;
SoftHdwSimulateImpl:
CEDAR
PROGRAM
IMPORTS BitOps, CDProperties, CDSequencerExtras, IO, SoftHdwAssembly, SoftHdwBasics, TerminalIO
EXPORTS SoftHdwSimulate
= BEGIN OPEN SoftHdwSimulate;
designToSimulationKey:
PUBLIC REF
INT ←
NEW[
INT];
Create:
PUBLIC
PROC [name: Rope.
ROPE, program: SoftHdwAssembly.Program, print:
BOOL ←
FALSE, useConnectionMachine:
BOOL ←
FALSE]
RETURNS [simulation: Simulation] = {
size: SoftHdwAssembly.Position ← SoftHdwAssembly.Size[program];
simulation ← NEW[SimulationRec];
simulation.sizes ← NEW[SoftHdwAssembly.ArrayPositionRec];
simulation.sizes.grain ← [4,4];
simulation.sizes.minorArray ← [16,16];
simulation.sizes.chip ← [1,1];
SELECT program.coordinates
FROM
MinorArray => simulation.sizes.minorArray ← size;
Chip => simulation.sizes.chip ← size;
ENDCASE => ERROR;
simulation.base ← SoftHdwBasics.CreateBase[simulation.sizes, useConnectionMachine];
simulation.program ← program;
IF print
THEN {
simulation.design ← SoftHdwAssembly.PrintAndDraw[simulation.sizes, program];
CDProperties.PutDesignProp[simulation.design, designToSimulationKey, simulation];
};
};
Initialize:
PUBLIC
PROC [simulation: Simulation] = {
ProgramTile: SoftHdwAssembly.EachTileProc = {
SoftHdwBasics.Store[simulation.base, position, TRUE];
};
SoftHdwBasics.Initialize[simulation.base];
SoftHdwAssembly.EnumerateTiles[simulation.program, ProgramTile];
};
Fetch:
PUBLIC
PROC [simulation: Simulation, position: SoftHdwBasics.ArrayPosition, time:
INT ← -1]
RETURNS [value:
BOOL] = {
value ← SoftHdwBasics.Fetch[simulation.base, position, time];
};
Store:
PUBLIC
PROC [simulation: Simulation, position: SoftHdwBasics.ArrayPosition, value:
BOOL] = {
SoftHdwBasics.Store[simulation.base, position, value];
};
MasterToSlave:
PUBLIC
PROC [simulation: Simulation] = {
SoftHdwBasics.MasterToSlave[simulation.base];
};
Relax:
PUBLIC
PROC [simulation: Simulation] = {
SoftHdwBasics.Relax[simulation.base];
};
Sample:
PUBLIC
PROC [simulation: Simulation] = {
SoftHdwBasics.Sample[simulation.base];
};
PrintArrayValue:
PROC [command: CDSequencer.Command] = {
simulation: Simulation ← NARROW[CDProperties.GetDesignProp[command.design, designToSimulationKey]];
ambiguous: BOOL;
position: SoftHdwBasics.ArrayPosition;
[ambiguous, position] ← SoftHdwAssembly.CDToArrayPosition[simulation.sizes, simulation.program.coordinates, command.sPos];
IF ambiguous THEN TerminalIO.PutRope["Ambiguous position\n"]
ELSE {
value: BOOL ← Fetch[simulation, position];
TerminalIO.PutF["%g = %g\n", IO.rope[SoftHdwBasics.ArrayPositionToRope[position]], IO.int[IF value THEN 1 ELSE 0]];
};
};
Test:
PROC = {
design: CD.Design ← SoftHdwAssembly.OpenDesign["SoftHdwSimTest.dale"];
{
input: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: Input,
orientation: Horizontal,
chip: [0,0],
minorArray: [0,0],
grain: [0, 0]]];
output: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: Output,
orientation: Vertical,
chip: [0,0],
minorArray: [0,0],
grain: [0, 0]]];
simpleProgram: SoftHdwAssembly.Program ← SoftHdwAssembly.LoadTile[design, "SimpleCell"];
simulation: Simulation ← Create["Simple Test", simpleProgram];
Initialize[simulation];
Store[simulation, input, TRUE];
Relax[simulation];
IF Fetch[simulation, output] THEN ERROR;
Store[simulation, input, FALSE];
Relax[simulation];
IF NOT Fetch[simulation, output] THEN ERROR;
};
{
input: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: Input,
orientation: Horizontal,
chip: [0,0],
minorArray: [2,0],
grain: [0, 3]]];
output: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: Input,
orientation: Vertical,
chip: [0,0],
minorArray: [0,0],
grain: [2, 0]]];
counter3: SoftHdwAssembly.Program ← SoftHdwAssembly.LoadTile[design, "Counter3"];
simulation: Simulation ← Create["Counter Test", counter3];
Initialize[simulation];
Store[simulation, input, TRUE]; -- assert carry in
Relax[simulation];
Sample[simulation];
FOR count:
INT
IN [0..8)
DO
FOR bit:
INT
IN [0..3)
DO
output.minorArray.x ← bit;
IF Fetch[simulation, output]#BitOps.EBFD[count, bit, 3] THEN ERROR;
ENDLOOP;
MasterToSlave[simulation];
Relax[simulation];
Sample[simulation];
ENDLOOP;
};
{
StoreWord:
PROC [address, data:
CARDINAL] = {
FOR bit:
INT
IN [0..3)
DO
writeAddress.grain.y ← bit;
Store[simulation, writeAddress, BitOps.EBFW[address, bit, 3]];
ENDLOOP;
writeAddress.grain.y ← 3;
Store[simulation, writeAddress, TRUE];
FOR bit:
INT
IN [0..4)
DO
writeData.grain.x ← bit;
Store[simulation, writeData, BitOps.EBFW[data, bit, 4]];
ENDLOOP;
Relax[simulation];
Sample[simulation];
MasterToSlave[simulation];
Store[simulation, writeAddress, FALSE];
};
FetchWord:
PROC [address:
CARDINAL]
RETURNS [data:
CARDINAL ← 0] = {
FOR bit:
INT
IN [0..3)
DO
readAddress.grain.y ← bit;
Store[simulation, readAddress, BitOps.EBFW[address, bit, 3]];
ENDLOOP;
readAddress.grain.y ← 3;
Store[simulation, readAddress, TRUE];
Relax[simulation];
Sample[simulation];
FOR bit:
INT
IN [0..4)
DO
readData.grain.x ← bit;
data ← BitOps.IBIW[Fetch[simulation, readData], data, bit, 4];
ENDLOOP;
Store[simulation, readAddress, FALSE];
};
writeAddress: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: Input,
orientation: Horizontal,
minorArray: [2, 1]]];
writeData: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: Input,
orientation: Vertical,
minorArray: [1, 0]]];
readAddress: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: Input,
orientation: Horizontal,
minorArray: [0, 1]]];
readData: SoftHdwAssembly.ArrayPosition ←
NEW[SoftHdwAssembly.ArrayPositionRec ← [
type: LeftDown,
orientation: Vertical,
minorArray: [1, 1]]];
ramEven: SoftHdwAssembly.Program ← SoftHdwAssembly.LoadTile[design, "RAMEvenTest"];
simulation: Simulation ← Create["RAMEven Test", ramEven, TRUE];
Initialize[simulation];
FOR adr:
INT
IN [0..8)
DO
StoreWord[adr, adr];
ENDLOOP;
FOR adr:
INT
IN [0..8)
DO
IF FetchWord[adr] # adr THEN ERROR;
ENDLOOP;
};
};
CDSequencerExtras.RegisterCommand[key: $RosemaryPlotSelectedWires, proc: PrintArrayValue, queue: doQueue];
END.