Base
ArrayPosition: TYPE = REF ArrayPositionRec;
ArrayPositionRec:
TYPE =
RECORD [
type: NodeType,
orientation: Orientation,
chip: Position,
minorArray: Position,
grain: Position];
NodeType:
TYPE = {Interchip, Long, OToP, RDToP, LUToP, LToP, PToI, PToRD, PToLU, PToL, Input, Output, LeftUp, RightDown, ORDToI, LUToLU, OLUToI, ORDToL, RDToRD, ORDToLU, LUToI, OLUToRD, LToI, RDToI, InverterEnabled, FlipFlopEnabled, Master, InputEnabled};
Orientation:
TYPE = {Vertical, Horizontal};
Position:
TYPE = DABasics.Position;
Interchip, Long, Output, LeftUp, and RightDown are not accessible through Fetch and Store in the actual hardware and they are not state bits in the hardware. Input is the slave of Master and is accessible when FlipFlopEnabled is asserted, otherwise it also is not a state bit and is not accessible.
interchip and all of the edge tiles belong to the minor array or chip to the left or up. The pin tiles belong to the chip up or down, or left or right, depending on the proper low order bit of grain. The orientation of inputEnabled refers to the orientation of the output to which the input is connected.
interchip, long
vertical: chip, minor.x, grain.x
horizontal: chip, minor.y, grain.y
OToP, RDToP, LUToP, LToP, PToI, PToRD, PToLU, PToL
vertical: chip, minor.x, grain.x, low order bit of grain.y
horizontal: chip, minor.y, low order bit of grain.x, grain.y
input, output, leftUp, rightDown, ORDToI, LUToLU, OLUToI, ORDToL, RDToRD, ORDToLU, LUToI, OLUToRD, LToI, RDToI, inverterEnabled, flipFlopEnabled, master
vertical: chip, minor, grain.x
horizontal: chip, minor, grain.y
inputEnabled
vertical: chip, minor, grain
horizontal: chip, minor, grain
ArrayBase: TYPE = REF ArrayBaseRec;
CreateBase:
PROC [sizes: ArrayPosition]
RETURNS [array: ArrayBase];
Ignores type and orientation. Uses the rest of the dimensions to size things.