<<>> <> <> <> <> <<>> DIRECTORY Core, RefTab, Rope, CoreFlat, DABasics, SoftHdwAssembly, SoftHdwBasics; SoftHdwCompiler: CEDAR DEFINITIONS = BEGIN <> FlatCell: TYPE = REF FlatCellRec; FlatCellRec: TYPE = RECORD [ root: Core.CellType, wires: RefTab.Ref]; -- maps CoreFlat.FlatWire to Primitive Primitives: TYPE = LIST OF Primitive; Primitive: TYPE = REF PrimitiveRec; PrimitiveRec: TYPE = RECORD [ flatCell: CoreFlat.FlatCellTypeRec, flatOutput: CoreFlat.FlatWire, flatClock: CoreFlat.FlatWire _ NIL, -- not NIL => sequential element negateOutput: BOOL, sinks: Primitives _ NIL, -- NIL => primary output or unused inputs: SEQUENCE size: CARDINAL OF PolarizedInputRec]; PolarizedInputs: TYPE = LIST OF PolarizedInputRec; PolarizedInputRec: TYPE = RECORD [ flatInput: CoreFlat.FlatWire, negate: BOOL, source: Primitive _ NIL]; -- NIL => primary input Placement: TYPE = REF PlacementRec; PlacementRec: TYPE = RECORD [ flatCell: FlatCell, sizes: ArrayPosition, maxChip: DABasics.Position, positions: RefTab.Ref]; -- maps Primitive to PrimitiveAssignment PrimitiveAssignment: TYPE = REF PrimitiveAssignmentRec; PrimitiveAssignmentRec: TYPE = RECORD [ position: ArrayPosition, inputIndicies: SEQUENCE size: CARDINAL OF CARDINAL]; ArrayPositions: TYPE = SoftHdwBasics.ArrayPositions; ArrayPosition: TYPE = SoftHdwBasics.ArrayPosition; ArrayPositionRec: TYPE = SoftHdwBasics.ArrayPositionRec; Orientation: TYPE = SoftHdwBasics.Orientation; Position: TYPE = SoftHdwBasics.Position; NodeType: TYPE = SoftHdwBasics.NodeType; WireNodeType: TYPE = NodeType[Input..RightUp]; Surface: TYPE = REF SurfaceRec; SurfaceRec: TYPE = RECORD [ sizes: ArrayPosition, nodes: ARRAY WireNodeType OF ARRAY Orientation OF NodeArrays]; NodeArrays: TYPE = RECORD [ base: NodeArray, maxNeighbors: DABasics.Number, nodeSize: DABasics.Number, grainSize: DABasics.Number, orientSize: DABasics.Number, chipXSize: DABasics.Number, chipYSize: DABasics.Number, minorXSize: DABasics.Number]; NodeArray: TYPE = RECORD [ pages: INT, base: LONG POINTER]; <<{Input, Output, LeftDown, RightUp} >> << {Horizontal} => ARRAY [grain.y, chip.x, chip.y, minor.x, minor.y] OF NodeRec>> << {Vertical} => ARRAY [grain.x, chip.x, chip.y, minor.x, minor.y] OF NodeRec>> <<{Long}>> <<{Horizontal} => ARRAY [grain.y, chip.x, chip.y, minor.y] OF NodeRec>> <<{Vertical} => ARRAY [grain.x, chip.x, chip.y, minor.x] OF NodeRec>> <<>> NodeLabel: TYPE = LONG POINTER; -- really CoreFlat.FlatWire Nodes: TYPE = LIST OF Node; Node: TYPE = LONG POINTER TO NodeRec; NodeRec: TYPE = RECORD [ fifoNext: Node, position: ArrayPositionRec, label: NodeLabel, back: Node, size: CARDINAL, neighbors: SEQUENCE COMPUTED CARDINAL OF Node]; <> Path: TYPE = REF PathRec; PathRec: TYPE = RECORD [ subPaths: SubPaths _ NIL, path: SEQUENCE size: CARDINAL OF ArrayPosition]; SubPaths: TYPE = REF SubPathsRec; SubPathsRec: TYPE = RECORD [ paths: SEQUENCE size: CARDINAL OF Path]; NetEndList: TYPE = LIST OF NetEnds; NetEnds: TYPE = REF NetEndsRec; NetEndsRec: TYPE = RECORD [ source: Node _ NIL, destinations: Nodes _ NIL]; RopeSequence: TYPE = REF RopeSequenceRec; RopeSequenceRec: TYPE = RECORD [ropes: SEQUENCE size: CARDINAL OF Rope.ROPE]; GrainPositions: TYPE = REF GrainPositionsRec; GrainPositionsRec: TYPE = RECORD [rows: SEQUENCE size: CARDINAL OF GrainRow]; GrainRow: TYPE = REF GrainRowRec; GrainRowRec: TYPE = RECORD [columns: SEQUENCE size: CARDINAL OF Primitive]; MinorArrays: TYPE = LIST OF MinorArray; MinorArray: TYPE = REF MinorArrayRec; MinorArrayRec: TYPE = RECORD [ rowIndex: CARDINAL _ 0, primitives: ARRAY Orientation OF GrainSequence _ ALL[NIL]]; GrainSequence: TYPE = REF GrainSequenceRec; GrainSequenceRec: TYPE = RECORD [ elements: SEQUENCE size: CARDINAL OF GrainRec]; GrainRec: TYPE = RECORD [ input: Primitive, inputIndex: CARDINAL, output: Primitive]; InputPositions: TYPE = LIST OF CARDINAL; <> Flatten: PROC [root: Core.CellType] RETURNS [flat: FlatCell]; HayBaler: PROC [flatCell: FlatCell, sizes: ArrayPosition, grainPositions: GrainPositions] RETURNS [placement: Placement]; TimberWolf: PROC [flatCell: FlatCell, sizes: ArrayPosition, attPerCell: INT _ 50] RETURNS [grainPositions: GrainPositions]; AddChannels: PROC [old: Placement, channelSize: NAT _ 1] RETURNS [new: Placement]; <> CreateSurfaceAndRoute: PROC [placement: Placement] RETURNS [route: RefTab.Ref, incompleteNetEnds: NetEndList, incomplete: INT _ 0]; <> DoRoutes: PROC [min, max: INT]; <> <<>> CheckRoute: PUBLIC PROC [route: RefTab.Ref]; <

> MarkedPlaceAndRoute: PROC [placement: Placement, route: RefTab.Ref, incompleteNetEnds: NetEndList, sizes: ArrayPosition]; ProgramFromPlaceAndRoute: PROC [placement: Placement, route: RefTab.Ref, incompleteNetEnds: NetEndList] RETURNS [program: SoftHdwAssembly.Program]; END.