DIRECTORY
CD, Core, CoreGeometry, DABasics, RefTab, Rope, Route, RTBasic, RTCoreUtil, RTSets, SC, Sinix;

SCPrivate: CEDAR DEFINITIONS = {

CompClass: TYPE = {other, logic, io, ft};
DegreeOfConnection: TYPE = {full, min, none};
UpperLowerConnection: TYPE = RECORD [
lower, upper: DegreeOfConnection _ none];
RouteTopology: TYPE = PACKED ARRAY MaxChanSr OF UpperLowerConnection;
LRSide: TYPE = DABasics.LRSide;
TBSide: TYPE = DABasics.TBSide;
LRSideSet: TYPE = RTSets.RTSmSet -- OF LRSide -- ;
SideSet: TYPE = RTSets.RTSmSet -- OF ValidSide -- ;
RowSet: TYPE = RTSets.RTLgSet -- OF MaxRowSr -- ;
ChanSet: TYPE = RTSets.RTLgSet -- OF MaxChanSr -- ;

StructureData: TYPE = REF StructureDataRec;
StructureDataRec: TYPE = RECORD [
instances: Instances _ NIL,
nets: RefTab.Ref _ NIL, -- maps CoreFlat canonical wires to corresponding net
sourceInstances: RefTab.Ref _ NIL -- maps FlatCellType to Instance for source flattened CT
];

LayoutData: TYPE = REF LayoutDataRec;
LayoutDataRec: TYPE = RECORD [
totWidth, totHeight, initTotWidth, initTotHeight: SC.Number _ 0,
bpRows: BpRows _ NIL,
lgRows: LgRows _ NIL,
sideChans: SideChans _ [NIL, NIL],
rowChans: RowChans _ NIL,
powerBuses: PowerBuses _ [NIL, NIL],
layoutParms: LayoutParms,
placeDat: REF ANY _ NIL,
globalRoute: REF ANY _ NIL];

Parms: TYPE = REF ParmsRec;
ParmsRec: TYPE = RECORD [
mode: Sinix.Mode _ NIL, -- the layout extraction mode, should be same as PWCore.extractMode
libName: Rope.ROPE _ NIL,
libDesign: CD.Design _ NIL,
ftObject, portObject, vddObject, gndObject: Object _ NIL];

LayoutParms: TYPE = REF LayoutParmsRec;
LayoutParmsRec: TYPE = RECORD [
whichFom: FomType _ wlFom,
useInteriorChanExits: BOOLEAN _ TRUE,
rowDirection: SC.Direction _ horizontal];

Object: TYPE = REF ObjectRec;
ObjectRec: TYPE = RECORD [
name: Rope.ROPE _ NIL, 
size, orgin: RTBasic.PQPos _ [0, 0], 
numPins: NAT _ 0,
pins: ObjectPins _ NIL, 
typeClass: CompClass _ other,
numTimesUsed: NAT _ 0,
cdOb: CD.Object _ NIL,
cellType: Core.CellType _ NIL];

ObjectPin: TYPE = REF ObjectPinRec;
ObjectPins: TYPE = REF ObjectPinsRec;
ObjectPinsRec: TYPE = RECORD [
p: SEQUENCE size: NAT OF ObjectPin];
ObjectPinRec: TYPE = RECORD [
name: Rope.ROPE _ NIL, 
pinPos: PinPos,
publicWire: Core.Wire,
rect: SC.Rect _ [0, 0, 0, 0],
layer: SC.Layer, 
equivClass: Rope.ROPE _ NIL];
PinPos: TYPE = RECORD [
side: SC.SideOrNone _ none, 
depth, location: SC.Number _ 0];

maxInstance: NAT = 12000;
MaxInstanceSr: TYPE = NAT[1 .. maxInstance];
ZMaxInstanceSr: TYPE = NAT[0 .. maxInstance];
Instance: TYPE = REF InstanceRec;
InstanceList: TYPE = LIST OF Instance;
Instances: TYPE = REF InstancesRec; 
InstancesRec: TYPE = RECORD [
count, numIOs, numLogics, numFts: ZMaxInstanceSr _ 0,
inst: Insts _ NIL]; 
Insts: TYPE = REF InstsOb;
InstsOb: TYPE = ARRAY MaxInstanceSr OF Instance _ ALL[NIL];
InstanceRec: TYPE = RECORD [
name: Rope.ROPE,
num: MaxInstanceSr,
object: Object _ NIL,
pinNets: PinNets _ NIL,
prePos, curPos, initPos, fnlPos: INT _ 0,
preOrien, curOrien, initOrien, fnlOrien: OrientationOrNone _ 0,
offset: SC.Number _ 0,
whichClass: CompClass,
ftNet: Net _ NIL,
equivPortClass: Rope.ROPE _ NIL,
instDat: REF ANY _ NIL,
preRow, curRow, initRow, fnlRow: ZMaxRowSr _ 0,
preSide, curSide, initSide, fnlSide: SC.SideOrNone _ none];

OrientationOrNone: TYPE = NAT[0 .. maxOrien];
Orientation: TYPE = OrientationOrNone[1 .. maxOrien];
maxOrien: NAT = 8;

PinNets: TYPE = REF PinNetsRec;
PinNetsRec: TYPE = RECORD[n: SEQUENCE size: NAT OF PinNet];
PinNet: TYPE = REF PinNetRec;
PinNetRec: TYPE = RECORD [
pin: ObjectPin _ NIL,
pinInChan: REF ANY _ NIL,		-- SCNewRoutePinsUtil.PinInChan
net: Net _ NIL];

PinType: TYPE = {compPin, externalPin, ftPin};
NetList: TYPE = LIST OF Net;
Net: TYPE = REF NetRec;
NetRec: TYPE = RECORD [
name: Rope.ROPE _ NIL,
publicWire: Core.Wire _ NIL,		-- Core wire for a public net, otherwise NIL
numberOfRegions: INT _ 0,		-- records number of breaks for this net
brokenNets: LIST OF Route.Label _ NIL,	-- records names of broken nets
trunkWidth, branchWidth: SC.Number _ 0,
score, oldScore: REAL _ 0.0, 		-- current and previous placement score
updatedOnTrial: INT _ 0,			-- placement trial last updated
externNet: BOOL _ FALSE, 		-- TRUE means this net is public, for publicWire
ftsOnRow: RowSet, 			-- rows which have ft's on this net
chanExits: ARRAY LRSide OF ChanSet,
routeTopology: RouteTopology,		-- global routing
netDat: REF ANY _ NIL,
pinsOnChan: LIST OF Route.Pin _ NIL,
segsInChan: LIST OF REF ANY _ NIL,		-- global route information for a channel
pins: NetPin _ NIL,			-- sequence of instance/pins on net
pinList:  REF ANY _ NIL,		-- pins for net in global routing (LIST OF SCNewRoutePinsUtil.PinInChan)
edgeList: REF ANY _ NIL			-- edges for net in global routing (SCNewGlobalRoute.EdgeList)
];

NetPin: TYPE = REF NetPinRec;
NetPinRec: TYPE = RECORD [
pinClass: PinType _ compPin,
instance: Instance _ NIL, 
pin: ObjectPin _ NIL,
link: NetPin _ NIL -- used to link pins on a net
];

maxPos: NAT = 1000;
MaxPosSr: TYPE = NAT[1 .. maxPos];
ZMaxPosSr: TYPE = NAT[0 .. maxPos];

BpRow: TYPE = REF BpRowRec;
BpRows: TYPE = REF BpRowsRec; 
BpRowsRec: TYPE = ARRAY SC.Side OF BpRow _ ALL[NIL]; 
BpRowRec: TYPE = RECORD [
bpSpacing: INT _ 0, 
size, sideOrg: RTBasic.PQPos _ [0, 0], 
dimInvalid: BOOLEAN _ TRUE, 
initMaxBpsOnSide, maxBpsOnSide, nBpsOnSide: ZMaxPosSr _ 0, 
bpsOnSide: ARRAY MaxPosSr OF Instance _ ALL[NIL], 
fnlBpFxd, initBpFxd: BOOLEAN _ FALSE];

maxLgRows: NAT = 200;
MaxRowSr: TYPE = NAT[1 .. maxLgRows];
ZMaxRowSr: TYPE = NAT[0 .. maxLgRows];
LgRow: TYPE = REF LgRowRec;
LgRows: TYPE = REF LgRowsRec;
LgRowsRec: TYPE = RECORD [
horzRowOrg, maxRowWidth: SC.Number _ 0,
numMaxRows: NAT _ 0,
count: ZMaxRowSr _ 0,
rows: ARRAY MaxRowSr OF LgRow _ ALL[NIL]]; 
LgRowRec: TYPE = RECORD [
size, rowOrg: RTBasic.PQPos _ [0, 0], 
dimInvalid: BOOLEAN _ TRUE,
rowNum: NAT, 
nLgsOnRow, nFtsOnRow: ZMaxPosSr _ 0, 
lgsOnRow: ARRAY MaxPosSr OF Instance _ ALL[NIL], 
fnlLgFxd, initLgFxd: BOOLEAN _ FALSE,
weight: NAT _ 0];

maxChans: NAT = maxLgRows + 1;
MaxChanSr: TYPE = NAT[1 .. maxChans];
ZMaxChanSr: TYPE = NAT[0 .. maxChans];

RowChan: TYPE = REF RowChanRec;
RowChans: TYPE = REF RowChansRec;
RowChansRec: TYPE = RECORD [
count: ZMaxChanSr _ 0,
chans: ARRAY MaxChanSr OF RowChan _ ALL[NIL]]; 
RowChanRec: TYPE = RECORD [
chanNum: NAT,
initChanWidth, chanWidth, chanPos, wireLength, chanDensity: SC.Number _ 0,
numTracks: NAT _ 0,
numExits: ARRAY LRSide OF ZMaxExitsSr _ [0, 0], 
exits: ExitArray _ NIL,
chanDat: REF ANY _ NIL
];
ExitArrayOb: TYPE = ARRAY LRSide OF ARRAY MaxExitsSr OF Exit;
ExitArray: TYPE = REF ExitArrayOb;
maxExits: NAT = 100;
MaxExitsSr: TYPE = NAT[1 .. maxExits];
ZMaxExitsSr: TYPE = NAT[0 .. maxExits];
Exit: TYPE = REF ExitRec;
ExitRec: TYPE = RECORD [
net: Net _ NIL,
pinInChan: REF ANY _ NIL,		-- SCNewRoutePinsUtil.PinInChan
pos: SC.Number _ 0,			-- track number
layer: SC.Layer];

SideChan: TYPE = REF SideChanRec;
SideChans: TYPE = ARRAY LRSide OF SideChan;
SideChanRec: TYPE = RECORD [
side: SC.Side,
initSideChanWidth, sideChanWidth, sideChanPos, wireLength: SC.Number _ 0,
sideChanTracks: NAT _ 0];

PowerBuses: TYPE = ARRAY LRSide OF PowerBus;
PowerBus: TYPE = REF PowerBusRec;
PowerBusRec: TYPE = RECORD [
name: Rope.ROPE _ NIL,
net: Net _ NIL];

FomType: TYPE = {areaFom, wlFom};

GetStructure: PROC [handle: SC.Handle, flattenCellType: RTCoreUtil.FlattenCellTypeProc]
RETURNS [done: BOOLEAN];

DestroyStructure: PROC [handle: SC.Handle];

SetUpLayout: PROC [handle: SC.Handle, cellType: Core.CellType]
RETURNS [done: BOOLEAN];

DestroyLayout: PROC [handle: SC.Handle];

DetailRoute: PROC [handle: SC.Handle] RETURNS [result: SC.Result];

PosImprove: PROC [handle: SC.Handle, whichFom: FomType, maxCycles: INT];
NewPosImprove:  PROC [handle: SC.Handle, whichFom: SCPrivate.FomType, maxCycles: INT];

NewOrientImprove: PUBLIC PROC [handle: SC.Handle, whichFom: SCPrivate.FomType, maxCycles: INT];

FTImprove: PROC [handle: SC.Handle, whichFom: FomType, maxCycles: INT];
OrientImprove: PROC [handle: SC.Handle, whichFom: FomType, maxCycles: INT];

SAInitialPlace: PROC [handle: SC.Handle, widthFactor: REAL, seed: INT] RETURNS [initialResult: SC.SAInitialResult];

SAGetParms: PROC [handle: SC.Handle, initialResult: SC.SAInitialResult, cellType: Core.CellType] RETURNS [saParms: SC.SAParms];
SAPlaceImprove: PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT];

SAPlaceImproveM: PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT];

PlaceImprove: PROC [handle: SC.Handle, maxCycles: INT];

SCRandomTest: PUBLIC PROC [handle: SC.Handle, trials, seed: INT];

}.



’SCPrivate.mesa
Copyright Σ 1985, 1986, 1987 by Xerox Corporation.  All rights reserved.
by Bryan Preas, July 10, 1985 11:48:30 am PDT 
Frank Bowers May 21, 1986 5:35:15 pm PDT
last edited by Bryan Preas, April 19, 1987 12:55:45 pm PDT
Jean-Marc Frailong October 14, 1987 6:02:23 pm PDT
Christian Le Cocq January 4, 1988 9:37:55 am PST

bonding pad and logic component types 
-- there is no way I can deal with an OVERLAID type....
compClassSel: SELECT OVERLAID CompClass FROM 
ft, logic => [
preRow, curRow, initRow, fnlRow: ZMaxRowSr _ 0],
ftNet: Net _ NIL],
io => [
preSide, curSide, initSide, fnlSide: SC.SideOrNone _ none],
equivPortClass: Rope.ROPE _ NIL],
ENDCASE];
interconnection net types 
bonding pad side and logic row types 
used to describe the bower nets
improve positions of cells on a row

improve positions of the feedthrus on a row

Initialize for simulated annealing improvement.
determine parameters for simulated placement.

Improve the placement for the instances (in pairs) by simulated annealing.
Improve the placement for the instances (one at a time) by simulated annealing.
Improve the placement for the instances by exhaustive search.
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