SCPrivate.mesa
Copyright Ó 1985, 1986, 1987 by Xerox Corporation. All rights reserved.
by Bryan Preas, July 10, 1985 11:48:30 am PDT
Frank Bowers May 21, 1986 5:35:15 pm PDT
last edited by Bryan Preas, April 19, 1987 12:55:45 pm PDT
Jean-Marc Frailong October 14, 1987 6:02:23 pm PDT
Christian Le Cocq January 4, 1988 9:37:55 am PST
DIRECTORY
CD, Core, CoreGeometry, DABasics, RefTab, Rope, Route, RTBasic, RTCoreUtil, RTSets, SC, Sinix;
SCPrivate: CEDAR DEFINITIONS = {
CompClass: TYPE = {other, logic, io, ft};
DegreeOfConnection: TYPE = {full, min, none};
UpperLowerConnection: TYPE = RECORD [
lower, upper: DegreeOfConnection ← none];
RouteTopology: TYPE = PACKED ARRAY MaxChanSr OF UpperLowerConnection;
LRSide: TYPE = DABasics.LRSide;
TBSide: TYPE = DABasics.TBSide;
LRSideSet: TYPE = RTSets.RTSmSet -- OF LRSide -- ;
SideSet: TYPE = RTSets.RTSmSet -- OF ValidSide -- ;
RowSet: TYPE = RTSets.RTLgSet -- OF MaxRowSr -- ;
ChanSet: TYPE = RTSets.RTLgSet -- OF MaxChanSr -- ;
StructureData: TYPE = REF StructureDataRec;
StructureDataRec: TYPE = RECORD [
instances: Instances ← NIL,
nets: RefTab.Ref ← NIL, -- maps CoreFlat canonical wires to corresponding net
sourceInstances: RefTab.Ref ← NIL -- maps FlatCellType to Instance for source flattened CT
];
LayoutData: TYPE = REF LayoutDataRec;
LayoutDataRec: TYPE = RECORD [
totWidth, totHeight, initTotWidth, initTotHeight: SC.Number ← 0,
bpRows: BpRows ← NIL,
lgRows: LgRows ← NIL,
sideChans: SideChans ← [NIL, NIL],
rowChans: RowChans ← NIL,
powerBuses: PowerBuses ← [NIL, NIL],
layoutParms: LayoutParms,
placeDat: REF ANYNIL,
globalRoute: REF ANYNIL];
Parms: TYPE = REF ParmsRec;
ParmsRec: TYPE = RECORD [
mode: Sinix.Mode ← NIL, -- the layout extraction mode, should be same as PWCore.extractMode
libName: Rope.ROPENIL,
libDesign: CD.Design ← NIL,
ftObject, portObject, vddObject, gndObject: Object ← NIL];
LayoutParms: TYPE = REF LayoutParmsRec;
LayoutParmsRec: TYPE = RECORD [
whichFom: FomType ← wlFom,
useInteriorChanExits: BOOLEANTRUE,
rowDirection: SC.Direction ← horizontal];
Object: TYPE = REF ObjectRec;
ObjectRec: TYPE = RECORD [
name: Rope.ROPENIL,
size, orgin: RTBasic.PQPos ← [0, 0],
numPins: NAT ← 0,
pins: ObjectPins ← NIL,
typeClass: CompClass ← other,
numTimesUsed: NAT ← 0,
cdOb: CD.Object ← NIL,
cellType: Core.CellType ← NIL];
ObjectPin: TYPE = REF ObjectPinRec;
ObjectPins: TYPE = REF ObjectPinsRec;
ObjectPinsRec: TYPE = RECORD [
p: SEQUENCE size: NAT OF ObjectPin];
ObjectPinRec: TYPE = RECORD [
name: Rope.ROPENIL,
pinPos: PinPos,
publicWire: Core.Wire,
rect: SC.Rect ← [0, 0, 0, 0],
layer: SC.Layer,
equivClass: Rope.ROPENIL];
PinPos: TYPE = RECORD [
side: SC.SideOrNone ← none,
depth, location: SC.Number ← 0];
bonding pad and logic component types
maxInstance: NAT = 12000;
MaxInstanceSr: TYPE = NAT[1 .. maxInstance];
ZMaxInstanceSr: TYPE = NAT[0 .. maxInstance];
Instance: TYPE = REF InstanceRec;
InstanceList: TYPE = LIST OF Instance;
Instances: TYPE = REF InstancesRec;
InstancesRec: TYPE = RECORD [
count, numIOs, numLogics, numFts: ZMaxInstanceSr ← 0,
inst: Insts ← NIL];
Insts: TYPE = REF InstsOb;
InstsOb: TYPE = ARRAY MaxInstanceSr OF Instance ← ALL[NIL];
InstanceRec: TYPE = RECORD [
name: Rope.ROPE,
num: MaxInstanceSr,
object: Object ← NIL,
pinNets: PinNets ← NIL,
prePos, curPos, initPos, fnlPos: INT ← 0,
preOrien, curOrien, initOrien, fnlOrien: OrientationOrNone ← 0,
offset: SC.Number ← 0,
whichClass: CompClass,
ftNet: Net ← NIL,
equivPortClass: Rope.ROPENIL,
instDat: REF ANYNIL,
-- there is no way I can deal with an OVERLAID type....
compClassSel: SELECT OVERLAID CompClass FROM
ft, logic => [
preRow, curRow, initRow, fnlRow: ZMaxRowSr ← 0],
ftNet: Net ← NIL],
io => [
preSide, curSide, initSide, fnlSide: SC.SideOrNone ← none],
equivPortClass: Rope.ROPENIL],
ENDCASE];
preRow, curRow, initRow, fnlRow: ZMaxRowSr ← 0,
preSide, curSide, initSide, fnlSide: SC.SideOrNone ← none];
OrientationOrNone: TYPE = NAT[0 .. maxOrien];
Orientation: TYPE = OrientationOrNone[1 .. maxOrien];
maxOrien: NAT = 8;
PinNets: TYPE = REF PinNetsRec;
PinNetsRec: TYPE = RECORD[n: SEQUENCE size: NAT OF PinNet];
PinNet: TYPE = REF PinNetRec;
PinNetRec: TYPE = RECORD [
pin: ObjectPin ← NIL,
pinInChan: REF ANYNIL,  -- SCNewRoutePinsUtil.PinInChan
net: Net ← NIL];
interconnection net types
PinType: TYPE = {compPin, externalPin, ftPin};
NetList: TYPE = LIST OF Net;
Net: TYPE = REF NetRec;
NetRec: TYPE = RECORD [
name: Rope.ROPENIL,
publicWire: Core.Wire ← NIL,  -- Core wire for a public net, otherwise NIL
numberOfRegions: INT ← 0,  -- records number of breaks for this net
brokenNets: LIST OF Route.Label ← NIL, -- records names of broken nets
trunkWidth, branchWidth: SC.Number ← 0,
score, oldScore: REAL ← 0.0,   -- current and previous placement score
updatedOnTrial: INT ← 0,   -- placement trial last updated
externNet: BOOLFALSE,   -- TRUE means this net is public, for publicWire
ftsOnRow: RowSet,    -- rows which have ft's on this net
chanExits: ARRAY LRSide OF ChanSet,
routeTopology: RouteTopology,  -- global routing
netDat: REF ANYNIL,
pinsOnChan: LIST OF Route.Pin ← NIL,
segsInChan: LIST OF REF ANYNIL,  -- global route information for a channel
pins: NetPin ← NIL,   -- sequence of instance/pins on net
pinList: REF ANYNIL,  -- pins for net in global routing (LIST OF SCNewRoutePinsUtil.PinInChan)
edgeList: REF ANYNIL   -- edges for net in global routing (SCNewGlobalRoute.EdgeList)
];
NetPin: TYPE = REF NetPinRec;
NetPinRec: TYPE = RECORD [
pinClass: PinType ← compPin,
instance: Instance ← NIL,
pin: ObjectPin ← NIL,
link: NetPin ← NIL -- used to link pins on a net
];
maxPos: NAT = 1000;
MaxPosSr: TYPE = NAT[1 .. maxPos];
ZMaxPosSr: TYPE = NAT[0 .. maxPos];
bonding pad side and logic row types
BpRow: TYPE = REF BpRowRec;
BpRows: TYPE = REF BpRowsRec;
BpRowsRec: TYPE = ARRAY SC.Side OF BpRow ← ALL[NIL];
BpRowRec: TYPE = RECORD [
bpSpacing: INT ← 0,
size, sideOrg: RTBasic.PQPos ← [0, 0],
dimInvalid: BOOLEANTRUE,
initMaxBpsOnSide, maxBpsOnSide, nBpsOnSide: ZMaxPosSr ← 0,
bpsOnSide: ARRAY MaxPosSr OF Instance ← ALL[NIL],
fnlBpFxd, initBpFxd: BOOLEANFALSE];
maxLgRows: NAT = 200;
MaxRowSr: TYPE = NAT[1 .. maxLgRows];
ZMaxRowSr: TYPE = NAT[0 .. maxLgRows];
LgRow: TYPE = REF LgRowRec;
LgRows: TYPE = REF LgRowsRec;
LgRowsRec: TYPE = RECORD [
horzRowOrg, maxRowWidth: SC.Number ← 0,
numMaxRows: NAT ← 0,
count: ZMaxRowSr ← 0,
rows: ARRAY MaxRowSr OF LgRow ← ALL[NIL]];
LgRowRec: TYPE = RECORD [
size, rowOrg: RTBasic.PQPos ← [0, 0],
dimInvalid: BOOLEANTRUE,
rowNum: NAT,
nLgsOnRow, nFtsOnRow: ZMaxPosSr ← 0,
lgsOnRow: ARRAY MaxPosSr OF Instance ← ALL[NIL],
fnlLgFxd, initLgFxd: BOOLEANFALSE,
weight: NAT ← 0];
maxChans: NAT = maxLgRows + 1;
MaxChanSr: TYPE = NAT[1 .. maxChans];
ZMaxChanSr: TYPE = NAT[0 .. maxChans];
RowChan: TYPE = REF RowChanRec;
RowChans: TYPE = REF RowChansRec;
RowChansRec: TYPE = RECORD [
count: ZMaxChanSr ← 0,
chans: ARRAY MaxChanSr OF RowChan ← ALL[NIL]];
RowChanRec: TYPE = RECORD [
chanNum: NAT,
initChanWidth, chanWidth, chanPos, wireLength, chanDensity: SC.Number ← 0,
numTracks: NAT ← 0,
numExits: ARRAY LRSide OF ZMaxExitsSr ← [0, 0],
exits: ExitArray ← NIL,
chanDat: REF ANYNIL
];
ExitArrayOb: TYPE = ARRAY LRSide OF ARRAY MaxExitsSr OF Exit;
ExitArray: TYPE = REF ExitArrayOb;
maxExits: NAT = 100;
MaxExitsSr: TYPE = NAT[1 .. maxExits];
ZMaxExitsSr: TYPE = NAT[0 .. maxExits];
Exit: TYPE = REF ExitRec;
ExitRec: TYPE = RECORD [
net: Net ← NIL,
pinInChan: REF ANYNIL,  -- SCNewRoutePinsUtil.PinInChan
pos: SC.Number ← 0,   -- track number
layer: SC.Layer];
SideChan: TYPE = REF SideChanRec;
SideChans: TYPE = ARRAY LRSide OF SideChan;
SideChanRec: TYPE = RECORD [
side: SC.Side,
initSideChanWidth, sideChanWidth, sideChanPos, wireLength: SC.Number ← 0,
sideChanTracks: NAT ← 0];
used to describe the bower nets
PowerBuses: TYPE = ARRAY LRSide OF PowerBus;
PowerBus: TYPE = REF PowerBusRec;
PowerBusRec: TYPE = RECORD [
name: Rope.ROPENIL,
net: Net ← NIL];
FomType: TYPE = {areaFom, wlFom};
GetStructure: PROC [handle: SC.Handle, flattenCellType: RTCoreUtil.FlattenCellTypeProc]
RETURNS [done: BOOLEAN];
DestroyStructure: PROC [handle: SC.Handle];
SetUpLayout: PROC [handle: SC.Handle, cellType: Core.CellType]
RETURNS [done: BOOLEAN];
DestroyLayout: PROC [handle: SC.Handle];
DetailRoute: PROC [handle: SC.Handle] RETURNS [result: SC.Result];
PosImprove: PROC [handle: SC.Handle, whichFom: FomType, maxCycles: INT];
improve positions of cells on a row
NewPosImprove: PROC [handle: SC.Handle, whichFom: SCPrivate.FomType, maxCycles: INT];
NewOrientImprove: PUBLIC PROC [handle: SC.Handle, whichFom: SCPrivate.FomType, maxCycles: INT];
FTImprove: PROC [handle: SC.Handle, whichFom: FomType, maxCycles: INT];
improve positions of the feedthrus on a row
OrientImprove: PROC [handle: SC.Handle, whichFom: FomType, maxCycles: INT];
SAInitialPlace: PROC [handle: SC.Handle, widthFactor: REAL, seed: INT] RETURNS [initialResult: SC.SAInitialResult];
Initialize for simulated annealing improvement.
SAGetParms: PROC [handle: SC.Handle, initialResult: SC.SAInitialResult, cellType: Core.CellType] RETURNS [saParms: SC.SAParms];
determine parameters for simulated placement.
SAPlaceImprove: PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT];
Improve the placement for the instances (in pairs) by simulated annealing.
SAPlaceImproveM: PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT];
Improve the placement for the instances (one at a time) by simulated annealing.
PlaceImprove: PROC [handle: SC.Handle, maxCycles: INT];
Improve the placement for the instances by exhaustive search.
SCRandomTest: PUBLIC PROC [handle: SC.Handle, trials, seed: INT];
}.