CoreClasses.recordCellClass => {
WritePublic:
PROC [publicWire: Core.Wire, name:
ROPE] = {
IF publicWire.size=0
THEN {
IF wireCount=0 THEN IO.PutRope[h.stream, "PARAMETER = "]
ELSE IO.PutRope[h.stream, ", "];
IO.PutRope[h.stream, name];
IF NOT RefTab.Insert[wireIDTab, publicWire, name] THEN ERROR;
wireCount ← wireCount+1;
}
ELSE
FOR i:
NAT
IN [0..publicWire.size)
DO
subWire: Core.Wire ← publicWire[i];
subName: ROPE ← PublicName[subWire, name, i];
WritePublic[subWire, subName];
ENDLOOP;
};
PublicName:
PROC [publicWire: Core.Wire, prefix:
ROPE, index:
NAT]
RETURNS [name:
ROPE] = {
name ← CoreOps.GetShortWireName[publicWire];
IF name=NIL THEN name ← Convert.RopeFromCard[from: index, showRadix: FALSE];
name ← Rope.Cat[prefix, "x", name];
};
WriteBind:
PROC [actual, public: Core.Wire, publicName:
ROPE] = {
IF actual.size>0
THEN
FOR i:
NAT
IN [0..actual.size)
DO
WriteBind[actual[i], public[i], PublicName[public[i], publicName, i]];
ENDLOOP
ELSE {
actualName: ROPE ← NARROW[RefTab.Fetch[wireIDTab, actual].val];
IF wireCount>0 THEN IO.PutRope[h.stream, ", "];
IO.PutRope[h.stream, publicName];
IO.PutRope[h.stream, "="];
IF actualName=
NIL
THEN {
actualName ← Rope.Cat["NUL%", Convert.RopeFromCard[from: idCount, showRadix: FALSE]];
idCount ← idCount + 1;
IF NOT RefTab.Insert[wireIDTab, actual, actualName] THEN ERROR;
};
IO.PutRope[h.stream, actualName];
wireCount ← wireCount+1;
};
};
wireIDTab: RefTab.Ref ← RefTab.Create[];
wireCount: NAT ← 0;
idCount: NAT ← 0;
rct: CoreClasses.RecordCellType ← NARROW[cellType.data];
IO.PutRope[h.stream, "\nMNAME = "];
IO.PutRope[h.stream, cellTypeInfo.name];
IO.PutRope[h.stream, ";\n"];
FOR i:
NAT
IN [0..cellType.public.size)
DO
subWire: Core.Wire ← cellType.public[i];
WritePublic[subWire, PublicName[subWire, NIL, i]];
ENDLOOP;
IF wireCount>0 THEN IO.PutRope[h.stream, ";\n"];
FOR instance:
NAT
IN [0..rct.size)
DO
subType: Core.CellType ← rct[instance].type;
subName: ROPE;
SELECT subType.class
FROM
CoreClasses.transistorCellClass => {
tran: CoreClasses.Transistor ← NARROW[subType.data];
subName ← CoreClasses.transistorTypeNames[tran.type];
};
CoreClasses.recordCellClass => {
subInfo: CellTypeInfo ← NARROW[RefTab.Fetch[h.cellTypeInfoTab, subType].val];
IF subInfo=NIL THEN subInfo ← GenInfo[subType];
subName ← subInfo.name;
};
ENDCASE => ERROR;
IO.PutRope[h.stream, subName];
wireCount ← 0;
IO.PutRope[h.stream, "("];
WriteBind[rct[instance].actual, subType.public, NIL];
IO.PutRope[h.stream, ");\n"];
ENDLOOP;
IO.PutRope[h.stream, "END;\n"];
FOR instance:
NAT
IN [0..rct.size)
DO
WriteCellType[h, rct[instance].type];
ENDLOOP;
};