DIRECTORY 
CD, CDIO, Core, CoreClasses, CoreDirectory, CoreOps, CoreProperties, IO, PWCore, Rope, RTTestUtil, SC;

SCTestCoreSmall: CEDAR PROGRAM

IMPORTS CDIO, CoreDirectory, CoreOps, CoreProperties, PWCore, RTTestUtil, SC
EXPORTS RTTestUtil = BEGIN

CreateCore: PUBLIC PROC [libName: Rope.ROPE] RETURNS [Core.CellType] =
BEGIN
coreLibrary: CoreDirectory.Library _ CoreDirectory.CreateLibrary[];
libDesign: CD.Design _ CDIO.ReadDesign[libName, NIL, CDIO.GetWorkingDirectory[]];
feedthruWires: Core.Wire _ RTTestUtil.CreateWire[LIST["FeedIn", "Vdd", "Gnd"]];
feedthru: Core.CellType _ RTTestUtil.CreateRecordCell["feedthru", feedthruWires, feedthruWires, NIL];
vddWires: Core.Wire _ RTTestUtil.CreateWire[LIST["Vdd", "Gnd"]];
vdd: Core.CellType _ RTTestUtil.CreateRecordCell["vdd", vddWires, vddWires, NIL];
gndWires: Core.Wire _ RTTestUtil.CreateWire[LIST["Vdd", "Gnd"]];
gnd: Core.CellType _ RTTestUtil.CreateRecordCell["gnd", gndWires, gndWires, NIL];
nandWires: Core.Wire _ RTTestUtil.CreateWire[LIST["I-A", "I-B", "X", "Vdd", "Gnd"]];
nand: Core.CellType _ RTTestUtil.CreateRecordCell["nand2", nandWires, nandWires, NIL];
pubWires:  Core.Wire _ RTTestUtil.CreateWire[LIST["BusTB", "BusLR", "Row1", "Row2", "Row3", "Row4", "Row5", "Col1", "Col2", "Col3", "Col4", "Col5", "nandInst15W", "nandInst25W", "nandInst35W", "nandInst45W", "nandInst55W", "Vdd", "Gnd"]];
internWires: Core.Wire _ RTTestUtil.UnionWire[pubWires, RTTestUtil.CreateWire[LIST["nandInst11W", "nandInst12W", "nandInst13W", "nandInst14W", "nandInst21W", "nandInst22W", "nandInst23W", "nandInst24W", "nandInst31W", "nandInst32W", "nandInst33W", "nandInst34W", "nandInst41W", "nandInst42W", "nandInst43W", "nandInst44W", "nandInst51W", "nandInst52W", "nandInst53W", "nandInst54W"]]];
nandInst11: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col1", "Row1", "nandInst11W", "Vdd", "Gnd"], nand, "nandInst11", internWires];
nandInst12: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col2", "nandInst11W", "nandInst12W", "Vdd", "Gnd"], nand, "nandInst12", internWires];
nandInst13: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col3", "nandInst12W", "nandInst13W", "Vdd", "Gnd"], nand, "nandInst13", internWires];
nandInst14: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col4", "nandInst13W", "nandInst14W", "Vdd", "Gnd"], nand, "nandInst14", internWires];
nandInst15: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col5", "nandInst14W", "nandInst15W", "Vdd", "Gnd"], nand, "nandInst15", internWires];
nandInst21: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col1", "Row2", "nandInst21W", "Vdd", "Gnd"], nand, "nandInst21", internWires];
nandInst22: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col2", "nandInst21W", "nandInst22W", "Vdd", "Gnd"], nand, "nandInst22", internWires];
nandInst23: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col3", "nandInst22W", "nandInst23W", "Vdd", "Gnd"], nand, "nandInst23", internWires];
nandInst24: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col4", "nandInst23W", "nandInst24W", "Vdd", "Gnd"], nand, "nandInst24", internWires];
nandInst25: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col5", "nandInst24W", "nandInst25W", "Vdd", "Gnd"], nand, "nandInst25", internWires];
nandInst31: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col1", "Row3", "nandInst31W", "Vdd", "Gnd"], nand, "nandInst31", internWires];
nandInst32: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col2", "nandInst31W", "nandInst32W", "Vdd", "Gnd"], nand, "nandInst32", internWires];
nandInst33: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col3", "nandInst32W", "nandInst33W", "Vdd", "Gnd"], nand, "nandInst33", internWires];
nandInst34: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col4", "nandInst33W", "nandInst34W", "Vdd", "Gnd"], nand, "nandInst34", internWires];
nandInst35: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col5", "nandInst34W", "nandInst35W", "Vdd", "Gnd"], nand, "nandInst35", internWires];
nandInst41: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col1", "Row4", "nandInst41W", "Vdd", "Gnd"], nand, "nandInst41", internWires];
nandInst42: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col2", "nandInst41W", "nandInst42W", "Vdd", "Gnd"], nand, "nandInst42", internWires];
nandInst43: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col3", "nandInst42W", "nandInst43W", "Vdd", "Gnd"], nand, "nandInst43", internWires];
nandInst44: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col4", "nandInst43W", "nandInst44W", "Vdd", "Gnd"], nand, "nandInst44", internWires];
nandInst45: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col5", "nandInst44W", "nandInst45W", "Vdd", "Gnd"], nand, "nandInst45", internWires];
nandInst51: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col1", "Row5", "nandInst51W", "Vdd", "Gnd"], nand, "nandInst51", internWires];
nandInst52: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col2", "nandInst51W", "nandInst52W", "Vdd", "Gnd"], nand, "nandInst52", internWires];
nandInst53: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col3", "nandInst52W", "nandInst53W", "Vdd", "Gnd"], nand, "nandInst53", internWires];
nandInst54: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col4", "nandInst53W", "nandInst54W", "Vdd", "Gnd"], nand, "nandInst54", internWires];
nandInst55: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["Col5", "nandInst54W", "nandInst55W", "Vdd", "Gnd"], nand, "nandInst55", internWires];
SCTest: Core.CellType _ RTTestUtil.CreateRecordCell["SCTest", pubWires, internWires, LIST[nandInst11, nandInst12, nandInst13, nandInst14, nandInst15, nandInst21, nandInst22, nandInst23, nandInst24, nandInst25, nandInst31, nandInst32, nandInst33, nandInst34, nandInst35, nandInst41, nandInst42, nandInst43, nandInst44, nandInst45, nandInst51, nandInst52, nandInst53, nandInst54, nandInst55]];
PWCore.SetGet[nand, libDesign];
PWCore.SetGet[feedthru, libDesign];
PWCore.SetGet[vdd, libDesign];
PWCore.SetGet[gnd, libDesign];
[] _ CoreDirectory.RegisterLibrary[coreLibrary,  libName];
[] _ CoreDirectory.Insert[coreLibrary,  "nand2", nand, TRUE];
[] _ CoreDirectory.Insert[coreLibrary,  "feedthru", feedthru, TRUE];
[] _ CoreDirectory.Insert[coreLibrary,  "vdd", vdd, TRUE];
[] _ CoreDirectory.Insert[coreLibrary,  "gnd", gnd, TRUE];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "BusTB"], SC.topSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "BusTB"], SC.bottomSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "BusLR"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "BusLR"], SC.leftSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row1"], SC.leftSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row2"], SC.leftSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row3"], SC.leftSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row4"], SC.leftSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row5"], SC.leftSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "BusLR"], SC.leftPositionProp, NEW[INT _ 10]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row1"], SC.leftPositionProp, NEW[INT _ 9]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row2"], SC.leftPositionProp, NEW[INT _ 8]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row3"], SC.leftPositionProp, NEW[INT _ 7]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row4"], SC.leftPositionProp, NEW[INT _ 6]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row5"], SC.leftPositionProp, NEW[INT _ 5]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row1"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row2"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row3"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row4"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row5"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "BusLR"], SC.rightPositionProp, NEW[INT _ 1]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row1"], SC.rightPositionProp, NEW[INT _ 5]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row2"], SC.rightPositionProp, NEW[INT _ 6]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row3"], SC.rightPositionProp, NEW[INT _ 7]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row4"], SC.rightPositionProp, NEW[INT _ 8]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Row5"], SC.rightPositionProp, NEW[INT _ 9]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col1"], SC.topSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col2"], SC.topSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col3"], SC.topSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col4"], SC.topSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col5"], SC.topSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col1"], SC.bottomSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col2"], SC.bottomSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col3"], SC.bottomSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col4"], SC.bottomSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Col5"], SC.bottomSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "nandInst15W"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "nandInst25W"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "nandInst35W"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "nandInst45W"], SC.rightSideProp, NEW[BOOL _ TRUE]];
CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "nandInst55W"], SC.rightSideProp, NEW[BOOL _ TRUE]];
RETURN [SCTest];
END;

END.

ÒSCTestCoreSmall.mesa
Copyright Ó 1985, 1987 by Xerox Corporation.  All rights reserved.
Frank Bowers December 19, 1985 10:36:54 am PST
Bryan Preas December 15, 1986 7:46:56 pm PST

Create a Core design

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