DIRECTORY
CD, CDSimpleRules, Core, CoreFlat, CoreGeometry, CoreOps, CoreProperties, CoreRoute, DABasics, Process, PWCore, Rope, Route, RTCoreUtil, SC, SCChanUtil, SCInitialPlace, SCInstUtil, -- SCExprGlobalRoute, -- SCNetUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCExtras, SCSmash, SCUtil, Sinix, SinixOps, Sisyph;

SCImpl: CEDAR PROGRAM 
IMPORTS CD, CDSimpleRules, CoreGeometry, CoreOps, CoreProperties, CoreRoute, Process, PWCore, Rope, Route, RTCoreUtil, SC, SCChanUtil, SCInitialPlace, SCInstUtil, -- SCExprGlobalRoute, --  SCNetUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCUtil, SinixOps, Sisyph
EXPORTS SC, SCExtras
SHARES SC = {

debug: BOOLEAN _ FALSE;
Error: PUBLIC ERROR[errorType: SC.ErrorType _ callingError, explanation: Rope.ROPE _ NIL] = CODE;
Signal: PUBLIC SIGNAL[signalType: SC.ErrorType _ callingError, explanation: Rope.ROPE _ NIL] = CODE;
CreateDesignRules: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction] RETURNS [designRules: SC.DesignRules] =

BEGIN
hLayer: CD.Layer _ CDSimpleRules.GetLayer[technologyKey, horizLayer];
vLayer: CD.Layer _ CDSimpleRules.GetLayer[technologyKey, vertLayer];
technology: CD.Technology _ CD.FetchTechnology[technologyKey];
designRules _ NEW[SC.DesignRulesRec _ [horizLayer: horizLayer, vertLayer: vertLayer, rowParms: Route.DefaultDesignRulesParameters[technology, hLayer, vLayer, rowDirection], sideParms: Route.DefaultDesignRulesParameters[technology, hLayer, vLayer, rowDirection]]];
designRules.rowRules _ Route.DefaultDesignRules[designRules.rowParms];
designRules.sideRules _ Route.DefaultDesignRules[designRules.sideParms];
END;
CreateHandle: PUBLIC PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE, designRules: SC.DesignRules, name: Rope.ROPE] RETURNS [handle: SC.Handle] ~ {
parms: SCPrivate.Parms _ NEW[SCPrivate.ParmsRec];
IF designRules = NIL THEN SC.Signal[callingError, "No design rules."];
IF cellType = NIL THEN SC.Signal[callingError, "No Core cell type."];
handle _ NEW[SC.HandleRec];
handle.name _ IF name # NIL THEN name ELSE CoreOps.GetCellTypeName[cellType];
handle.rules _ designRules;
handle.coreCellType _ cellType;
parms.libName _ libName; 
parms.mode _ SinixOps.GetExtractMode[designRules.rowParms.technology];
IF parms.mode#PWCore.extractMode THEN SC.Signal[callingError, "PWCore extractMode does not agree with specified technology"];
handle.parms _ parms;
IF ~SCPrivate.SetUpLayout[handle, cellType] THEN SC.Signal[callingError, "Unable to construct layout data"];
IF ~SCPrivate.GetStructure[handle, flattenCellType] THEN SC.Signal[callingError, "Unable to construct structure data"];
CoreProperties.PutCellTypeProp[cellType, SC.handleAtom, handle];
};

InitialPlace: PUBLIC PROC [handle: SC.Handle, numRows: NAT _ 0] = {
layoutData: SCPrivate.LayoutData _ NARROW[handle.layoutData];
p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCSmash.RemoveSmash[handle];
SCPlaceUtil.ClrCurPlac[handle, TRUE];
SCInitialPlace.PrePlace[handle: handle, numRows: numRows, routingFactor: 2.5, initialized: TRUE];
SCInitialPlace.RowInit[handle];
SCInitialPlace.PosInit[handle];
[layoutData.lgRows.maxRowWidth, layoutData.lgRows.numMaxRows] _ SCRowUtil.FindMaxRow[handle];
SCChanUtil.InitChanWidths[handle];
SCInstUtil.AsgnChanPos[handle];
layoutData.initTotWidth _ layoutData.totWidth;
layoutData.initTotHeight _ layoutData.totHeight;

IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
[] _ SCUtil.WriteResults["End initial placement\n initial size: ", handle, 0];
Process.SetPriority[p]}; 

GlobalRoute: PUBLIC PROC [handle: SC.Handle] = {
p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCSmash.RemoveSmash[handle];
SCSmash.SmashAllNets[handle, FALSE];
Process.SetPriority[p]};


DetailRoute: PUBLIC PROC [handle: SC.Handle] RETURNS [result: SC.Result] = {
p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
result _ SCPrivate.DetailRoute[handle];
Process.SetPriority[p]};


Destroy: PUBLIC PROC [handle: SC.Handle] ~ {
SCPrivate.DestroyLayout[handle];
SCPrivate.DestroyStructure[handle];
SCUtil.DestroyRules[handle];
SCUtil.DestroyParms[handle];
CoreProperties.PutCellTypeProp[handle.coreCellType, SC.handleAtom, NIL]; -- remove handle
handle^ _ [];
};
StandardCellRoute: PWCore.LayoutProc = {
hMaterial: Rope.ROPE _ "metal";
vMaterial: Rope.ROPE _ "metal2";
widthFactor: REAL _ MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules _ SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];
handle: SC.Handle _ SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules];
SCUtil.ReadTWPlace[handle: handle];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
SC.GlobalRoute[handle];
obj _ SC.DetailRoute[handle].object;
};

StandardCellLayoutTW: PWCore.LayoutProc = {
twMsg: Rope.ROPE;
hMaterial: Rope.ROPE _ "metal";
vMaterial: Rope.ROPE _ "metal2";
widthFactor: REAL _ MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules _ SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];
handle: SC.Handle _ SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
SCUtil.WriteTWFiles[handle: handle];
twMsg _ SCUtil.TWIt[handle.name];
IF twMsg#NIL THEN SC.Error[callingError, Rope.Cat[twMsg, ", Problem on Unix Placement Server. Check file ", handle.name, ".out"]];
SCUtil.ReadTWPlace[handle: handle];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
SC.GlobalRoute[handle];
obj _ SC.DetailRoute[handle].object;
};

StandardCellDecorate: PUBLIC PWCore.DecorateProc = {

WireToLabels: PROC [wire: Core.Wire] RETURNS [LIST OF Route.Label] ~ {
net: SCPrivate.Net _ SCNetUtil.FindPublicNet[handle, wire];
RETURN[IF net.numberOfRegions <= 0 THEN LIST[net.name] ELSE net.brokenNets]};

ComparePos: PROC [pos1, pos2: CD.Position] RETURNS [BOOL]  ~ {
IF pos1.y = pos2.y THEN RETURN[pos1.x < pos2.x]
ELSE RETURN[pos1.y < pos2.y]};

CompareCT: CoreRoute.CompareFlatCTProc ~ {
instance1: SCPrivate.Instance = SCInstUtil.FindSourceInstance[handle, NEW [CoreFlat.FlatCellTypeRec _ flatCT1]];
instance2: SCPrivate.Instance = SCInstUtil.FindSourceInstance[handle, NEW [CoreFlat.FlatCellTypeRec _ flatCT2]];
IF instance1.curRow = instance2.curRow THEN RETURN[instance1.curPos < instance2.curPos]
ELSE RETURN[instance1.curRow < instance2.curRow]};

handle: SC.Handle _ NARROW[CoreProperties.GetCellTypeProp[cellType, SC.handleAtom]];
IF handle # NIL THEN {
SmashPins: PROC [wire: Core.Wire] = {
CoreGeometry.PutPins[mode.decoration, wire, NIL];
};
mode: Sinix.Mode = NARROW [handle.parms, SCPrivate.Parms].mode;
CoreOps.VisitRootAtomics[cellType.public, SmashPins];
CoreRoute.DecorateRoutedArea[cellType: cellType, obj: obj, wireToLabels: WireToLabels,
compareIR: CoreRoute.CompareXorYStack, compareCT: CompareCT];
SC.Destroy[handle]}};

StandardCellAttibutes: PUBLIC PWCore.AttributesProc = {-- [cellType: Core.CellType]

SideAndPositionForPin: PROC [wire: Core.Wire, side: DABasics.Side, index: INT] = {

PushPropOnAtomic: PROC [wire: Core.Wire] ~ {
sideVal: REF ANY _ CoreProperties.GetWireProp[wire, sideProp];
positionVal: REF ANY _ CoreProperties.GetWireProp[wire, positionProp];
IF sideVal = NIL THEN CoreProperties.PutWireProp[wire, sideProp, NEW[BOOL _ TRUE]];
IF positionVal = NIL THEN CoreProperties.PutWireProp[wire, positionProp, NEW[INT _ index]]};

sideProp: ATOM _ SELECT side FROM
bottom => bottomSideProp,
top => topSideProp,
right => rightSideProp,
left => leftSideProp,
ENDCASE => SC.Error[programmingError, "Not suppose to happen."];
positionProp: ATOM _ SELECT side FROM
bottom => bottomPositionProp,
top => topPositionProp,
right => rightPositionProp,
left => leftPositionProp,
ENDCASE => SC.Error[programmingError, "Not suppose to happen."];
IF wire.size=0 THEN PushPropOnAtomic[wire] 
ELSE CoreOps.VisitRootAtomics[wire, PushPropOnAtomic]};

DO
IF CoreGeometry.HasObject[Sisyph.mode.decoration, cellType] THEN {
FOR side: DABasics.Side IN DABasics.Side DO
wires: Core.Wires _ CoreRoute.OrderedAtomicSchWires[cellType: cellType, side: side];
index: INT _ 0;
FOR wireList: Core.Wires _ wires, wireList.rest WHILE wireList # NIL DO
index _ index + 1;
SideAndPositionForPin[wireList.first, side, index];
ENDLOOP;
ENDLOOP;
CoreRoute.FlushSchPinCache[cellType: cellType];
EXIT};
IF cellType.class.recast = NIL THEN EXIT;
cellType _ CoreOps.Recast[cellType]
ENDLOOP}; 

SCRouteAtom: ATOM _ PWCore.RegisterLayoutAtom[$SCRoute, StandardCellRoute, StandardCellDecorate, StandardCellAttibutes];
SCTWAtom: ATOM _ PWCore.RegisterLayoutAtom[$SCRemote, StandardCellLayoutTW, StandardCellDecorate, StandardCellAttibutes];



technologyKey: PUBLIC ATOM _ $cmosB;		-- $cmosA or $cmosB
libName: PUBLIC Rope.ROPE _ "CMOSB";
numRows: PUBLIC ATOM _ $numRows;

rowProp: PUBLIC ATOM _ $Row;

positionProp: PUBLIC ATOM _ $Position;
bottomSideProp: PUBLIC ATOM _ $BottomSide;
rightSideProp: PUBLIC ATOM _ $RightSide;
topSideProp: PUBLIC ATOM _ $TopSide;
leftSideProp: PUBLIC ATOM _ $LeftSide;

bottomPositionProp: PUBLIC ATOM _ $BottomPosition;
rightPositionProp: PUBLIC ATOM _ $RightPosition;
topPositionProp: PUBLIC ATOM _ $TopPosition;
leftPositionProp: PUBLIC ATOM _ $LeftPosition;

usePublicPositionsProp: PUBLIC ATOM _ $UsePublicPositions;

bottomMaxExits: PUBLIC ATOM _ $BottomMaxExits;
rightMaxExits: PUBLIC ATOM _ $RightMaxExits;
topMaxExits: PUBLIC ATOM _ $TopMaxExits;
leftMaxExits: PUBLIC ATOM _ $LeftMaxExits;

bottomExitSpacing: PUBLIC ATOM _ $BottomExitSpacing;
rightExitSpacing: PUBLIC ATOM _ $RightExitSpacing;
topExitSpacing: PUBLIC ATOM _ $TopExitSpacing;
leftExitSpacing: PUBLIC ATOM _ $LeftExitSpacing;
investmentProp: PUBLIC ATOM _ $Investment;
veryLongValue: PUBLIC ATOM _ $veryLong;
longValue: PUBLIC ATOM _ $long;
mediumValue: PUBLIC ATOM _ $medium;
shortValue: PUBLIC ATOM _ $short;
veryShortValue: PUBLIC ATOM _ $veryShort;

t0SA: PUBLIC ATOM _ $t0SA;
maxTStepSA: PUBLIC ATOM _ $maxTStepSA;
lambdaSA: PUBLIC ATOM _ $lambdaSA;
tableSizeSA: PUBLIC ATOM _ $tableSizeSA;
limitSA: PUBLIC ATOM _ $limitSA;

widthFactorProp: PUBLIC ATOM _ $widthFactor;
handleAtom: PUBLIC ATOM _ CoreProperties.RegisterProperty[$SCHandle];

interestingProperties: PUBLIC RTCoreUtil.PropertyKeys _ NEW[RTCoreUtil.PropertyKeysRec[27]];
interestingProperties.p[0] _ numRows;
interestingProperties.p[1] _ rowProp;
interestingProperties.p[2] _ positionProp;
interestingProperties.p[3] _ bottomSideProp;
interestingProperties.p[4] _ rightSideProp;
interestingProperties.p[5] _ topSideProp;
interestingProperties.p[6] _ leftSideProp;
interestingProperties.p[7] _ bottomPositionProp;
interestingProperties.p[8] _ rightPositionProp;
interestingProperties.p[9] _ topPositionProp;
interestingProperties.p[10] _ leftPositionProp;
interestingProperties.p[11] _ usePublicPositionsProp;
interestingProperties.p[12] _ bottomMaxExits;
interestingProperties.p[13] _ rightMaxExits;
interestingProperties.p[14] _ topMaxExits;
interestingProperties.p[15] _ leftMaxExits;
interestingProperties.p[16] _ bottomExitSpacing;
interestingProperties.p[17] _ rightExitSpacing;
interestingProperties.p[18] _ topExitSpacing;
interestingProperties.p[19] _ leftExitSpacing;
interestingProperties.p[20] _ investmentProp;
interestingProperties.p[21] _ t0SA;
interestingProperties.p[22] _ maxTStepSA;
interestingProperties.p[23] _ lambdaSA;
interestingProperties.p[24] _ limitSA;
interestingProperties.p[25] _ widthFactorProp;
interestingProperties.p[26] _ handleAtom;
}. 




.าSCImpl.mesa
Copyright ำ 1985, 1986, 1987 by Xerox Corporation.  All rights reserved.
Bryan Preas, August 14, 1986 5:07:05 pm PDT 
Last Edited by: Bryan Preas June 15, 1987 6:21:04 pm PDT
Don Curry February 24, 1988 9:40:02 am PST
Jean-Marc Frailong October 14, 1987 6:12:37 pm PDT
Cong, August 25, 1987 8:07:27 pm PDT
Christian Le Cocq February 3, 1988 3:32:13 pm PST
Errors
Design Rules
Define the standard cell design rules.  technologyKey values are predefinded for now. horizLayer, vertLayer should be "poly", "metal" or "metal2".
Standard Cell Handles and Results
Create a standard cell design.  The standard cell design definition includes the design rules (conductor and via widths and spacings) and the circuit definition. The returned handle is also setup as a property on the cell type for the benefit of the decorate proc...
Set up the layout data
Set up the structure data
Standard Cell Optimization and Construction
Determine an initial placement for the instances.

PosImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the positions of instances whithin rows.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.PosImprove[handle, areaFom, maxCycles];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

PosImproveWL: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the positions of instances whithin rows using wire lenght as figure of merit.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.PosImprove[handle, wlFom, maxCycles];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

OrientImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the orientation of instances.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.OrientImprove[handle, areaFom, maxCycles];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

OrientImproveWL: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the orientation of instances using wire lenght as figure of merit.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.OrientImprove[handle, wlFom, maxCycles];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

FTImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the positions of instances whithin rows.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.FTImprove[handle, wlFom, maxCycles];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

SAInitialPlace: PUBLIC PROC [handle: SC.Handle, widthFactor: REAL, seed: INT] RETURNS [initialResult: SC.SAInitialResult] = {
Initialize for simulated annealing improvement.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
initialResult _ SCPrivate.SAInitialPlace[handle, widthFactor, seed];
Process.SetPriority[p]};

SAGetParms: PUBLIC PROC [handle: SC.Handle, initialResult: SC.SAInitialResult, cellType: Core.CellType] RETURNS [saParms: SC.SAParms] = {
determine parameters for simulated placement.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
saParms _ SCPrivate.SAGetParms[handle, initialResult, cellType];
Process.SetPriority[p]};

SAPlaceImprove: PUBLIC PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT] = {
Improve the placement for the instances (one at a time) by simulated annealing.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.SAPlaceImprove[handle, saParms, widthFactor, seed];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

SAPlaceImproveM: PUBLIC PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT] = {
Improve the placement for the instances (one at a time) by simulated annealing.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.SAPlaceImproveM[handle, saParms, widthFactor, seed];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

PlaceImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {
Improve the placement for the instances by exhaustive search.

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCPrivate.PlaceImprove[handle, maxCycles];
IF debug THEN SCPlaceUtil.WriteCurPlace[handle];
Process.SetPriority[p]};

Determine strategic paths for the wiring that must cross cell rows.

ExprGlobalRoute: PUBLIC PROC [handle: SC.Handle] = {
Determine strategic paths for the wiring that must cross cell rows.
Uses minimum Stiener tree global routing

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
SCExprGlobalRoute.GlobalRouteAllNets[handle];
Process.SetPriority[p]};
Determine actual wiring paths.  

ExprDetailRoute: PUBLIC PROC [handle: SC.Handle] RETURNS [result: SC.Result] = {
Determine actual wiring paths.
Works with ExprGlobalRoute  

p: Process.Priority _ Process.GetPriority[];
Process.SetPriority[Process.priorityBackground];
result _ SCExprGlobalRoute.DetailRoute[handle];
Process.SetPriority[p]};

CreateLayout: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, numRows: NAT, cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE _ NIL, name: Rope.ROPE _ NIL] RETURNS [object: CD.Object] = {
Create a standard cell object by performing the above operations

widthFactor: REAL _ MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

designRules: SC.DesignRules _ SC.CreateDesignRules[technologyKey, horizLayer, vertLayer, rowDirection];
handle: SC.Handle _ SC.CreateHandle[cellType, flattenCellType, libName, designRules, name];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
SC.SAPlaceImprove[handle, SC.SAGetParms[handle, SC.SAInitialPlace[handle, widthFactor], cellType], widthFactor];
SC.GlobalRoute[handle];
object _ SC.DetailRoute[handle].object;
};
Remove circular references so garbage collection can work

PWCore Interface
The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell router.  Placement is obtained from timberwolf.
The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell router.  Placement is obtained from timberwolf.
StandardCellRouteX: PWCore.LayoutProc = {
hMaterial: Rope.ROPE _ "metal";
vMaterial: Rope.ROPE _ "metal2";
widthFactor: REAL _ MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules _ SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];
handle: SC.Handle _ SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules];
SCUtil.ReadTWPlace[handle: handle];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
SCExprGlobalRoute.GlobalRouteAllNets[handle];
obj _ SC.ExprDetailRoute[handle].object;
};

The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.
StandardCellLayout: PWCore.LayoutProc = {
saParms: SC.SAParms;
initialResult: SC.SAInitialResult;
hMaterial: Rope.ROPE _ "metal";
vMaterial: Rope.ROPE _ "metal2";
widthFactor: REAL _ MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules _ SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];
handle: SC.Handle _ SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
initialResult _ SC.SAInitialPlace[handle, widthFactor];
saParms _ SC.SAGetParms[handle, initialResult, cellType];
SC.SAPlaceImprove[handle: handle, saParms: saParms, widthFactor: widthFactor];
SC.GlobalRoute[handle];
obj _ SC.DetailRoute[handle].object;
};

The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.
SC.ExprGlobalRouteAllNets[handle];
The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the TimberWolf standard cell placer and SC router.  Uses an experimental version of the Global Router
StandardCellLayoutTWX: PWCore.LayoutProc = {
twMsg: Rope.ROPE;
hMaterial: Rope.ROPE _ "metal";
vMaterial: Rope.ROPE _ "metal2";
widthFactor: REAL _ MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules _ SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];
handle: SC.Handle _ SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
SCUtil.WriteTWFiles[handle: handle];
twMsg _ SCUtil.TWIt[handle.name];
IF twMsg#NIL THEN SC.Error[callingError, Rope.Cat[twMsg, ", Problem on Unix Placement Server. Check file ", handle.name, ".out"]];
SCUtil.ReadTWPlace[handle: handle];
SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];
SCExprGlobalRoute.GlobalRouteAllNets[handle];
obj _ SC.ExprDetailRoute[handle].object;
};

PROC [cellType: CellType, obj: Object];
call back proc to map wires to labels
Called only for atomic publics
call back proc to order objects
call back proc to order cellTypes
PROC [root: Core.CellType, flatCT1, flatCT2: CoreFlat.FlatCellTypeRec] RETURNS [BOOL];
Puts on public wires their side as a property
process wire on side at index 
this cellType has decorations, run through the pins on the sides
SCLayoutAtom: ATOM _ PWCore.RegisterLayoutAtom[$SC, StandardCellLayout, StandardCellDecorate, StandardCellAttibutes];
Experimental Layout ATOMS
SCRouteXAtom: ATOM _ PWCore.RegisterLayoutAtom[$SCRouteX, StandardCellRouteX, StandardCellDecorate, StandardCellAttibutes];
SCTWXAtom: ATOM _ PWCore.RegisterLayoutAtom[$SCRemoteX, StandardCellLayoutTWX, StandardCellDecorate, StandardCellAttibutes];
Properties
row and logic cell properties
Used to specify the number of rows for a standard cell assembly.  Should be a property on Core cellType being laid out
Used to specify the row on which a logic cell is to be placed. rowProp and and INT row number should be a property/value on a logic cell insatance
Used to specify the position of a logic within a row or of an public pin on a side.  Should be used with INT value on logic cell instance.

side and public properties
Used to specify the side on which a public pin is to be placed.  (mumble)SideProp should be a TRUE on a public wire if it is to appear on (mumble) side
Used to specify the position (INT) in which a public pin is to be placed on a side.  (mumble)SideProp must be true on that side; should be a property/value on a public wire
Used to specify the position of a public in the schematic is to be retained int the layout; value must be TRUE
Used to specify the maximum number or publics on a side.
Used to specify the HINT for publics spacing on a side.

placement properties
Used to specify the investment to make in placement.
Used to specify simulated aneealing partameters to be used for placement
specifies the allowed length of the longest row compared to the minimun distance longest row

internal use
for internal use only
Cedar does not allow initialization of a sequence in the NEW!
Used to specify all the properties that are interesting to SC
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