DIRECTORY CMosB, DesignRules, Saguaro;

VTIRulesImpl: CEDAR PROGRAM
IMPORTS CMosB, DesignRules, Saguaro
= BEGIN OPEN DesignRules;



Generate: PROC = {
rules: Rules _ NewRules[$VTI, CMosB.cmosB, 1, 1];
gate: Layer _ NewLayer[rules, $Gate, "?", "Gate", "Defines gate area of p and n channel devices", Saguaro.gate];
nWell: Layer _ NewLayer[rules, $NWell, "CNW", "N- well", "Defines substrate of P channel devices", CMosB.nwell];
pDif: Layer _ NewLayer[rules, $PDif, "CPD", "P+ well diffusion", "Defines P+ diffused areas when diffusion does not contact substrate or well", CMosB.pdif];
pWellDif: Layer _ NewLayer[rules, $PWellDif, "CPD", "P+ substrate contact", "Defines P+ diffused areas when diffusion contacts substrate", CMosB.pwellCont];
nDif: Layer _ NewLayer[rules, $NDif, "CND", "N+ diffusion", "Defines N+ diffused areas when diffusion does not contact substrate or well", CMosB.ndif];
nWellDif: Layer _ NewLayer[rules, $NWellDif, "CND", "N+ well contact", "Defines N+ diffused areas when diffusion contacts well", CMosB.nwellCont];
poly: Layer _ NewLayer[rules, $Poly, "CP", "Polysilicon", "Defines poly gates and poly interconnect", CMosB.pol];
contact: Layer _ NewLayer[rules, $Contact, "CC", "Contact", "Defines contact openings to diffusion and poly", CMosB.cut];
metal1: Layer _ NewLayer[rules, $Metal1, "CM", "Metal 1", "Defines first metal interconnects", CMosB.met];
via: Layer _ NewLayer[rules, $Via, "CC2", "Via", "Defines openings in the insulator between first and second metal", CMosB.cut2];
metal2: Layer _ NewLayer[rules, $Metal2, "CC2", "Metal 2", "Defines second metal interconnects", CMosB.met2];
pad: Layer _ NewLayer[rules, $Pad, "CG", "Pad Window 1", "Defines openings on the passivation layer for probing and bonding", CMosB.ovg];
NewRule[rules, $NWellWidth, width, nWell, NIL, 4, "6.1.1"];
NewRule[rules, $NWellSamePotentialSpace, special, nWell, NIL, 4, "6.1.2.1"];
NewRule[rules, $NWellSpace, intraspace, nWell, NIL, 12, "6.1.2.2"];
NewRule[rules, $NWellOverlapsMetal1Pad, special, NIL, NIL, 0, "6.1.3.3"];
NewRule[rules, $NDifWidth, width, nDif, NIL, 2, "6.3.1"];
NewRule[rules, $PDifWidth, width, pDif, NIL, 2, "6.3.1"];
NewRule[rules, $NWellDifWidth, width, nWellDif, NIL, 2, "6.3.1"];
NewRule[rules, $PWellDifWidth, width, pWellDif, NIL, 2, "6.3.1"];
NewRule[rules, $NDifWhenPWellDifOneSideWidth, special, nDif, NIL, 3, "See Jeff"];
NewRule[rules, $PDifWhenNWellDifOneSideWidth, special, pDif, NIL, 3, "See Jeff"];
NewRule[rules, $NDifWhenPWellDifBothSidesWidth, special, nDif, NIL, 4, "See Jeff"];
NewRule[rules, $PDifWhenNWellDifBothSidesWidth, special, pDif, NIL, 4, "See Jeff"];
NewRule[rules, $NTransistorChannelWidth, special, nDif, poly, 3, "6.3.2"];
NewRule[rules, $PTransistorChannelWidth, special, pDif, poly, 3, "6.3.2"];
NewRule[rules, $NDifSpace, intraspace, nDif, NIL, 35, "6.3.3", 10];
NewRule[rules, $PDifSpace, intraspace, pDif, NIL, 35, "6.3.3", 10];
NewRule[rules, $NWellDifSpace, intraspace, nWellDif, NIL, 35, "6.3.3", 10];
NewRule[rules, $PWellDifSpace, intraspace, pWellDif, NIL, 35, "6.3.3", 10];

NewRule[rules, $NDifPDifSpace, interspace, nDif, pDif, 35, "6.3.3", 10];
NewRule[rules, $NDifNWellDifSpace, interspace, nDif, nWellDif, 35, "6.3.3", 10];
NewRule[rules, $PDifPWellDifSpace, interspace, pDif, pWellDif, 35, "6.3.3", 10];
NewRule[rules, $NWellDifPWellDifSpace, interspace, nWellDif, pWellDif, 35, "6.3.3", 10];
NewRule[rules, $NDifPWellDifSpace, interspace, nDif, pWellDif, 35, "6.3.3", 10];
NewRule[rules, $PDifNWellDifSpace, interspace, pDif, nWellDif, 35, "6.3.3", 10];
NewRule[rules, $NDifPWellDifSamePotentialSpace, special, nDif, pWellDif, 0, "6.3.4"];
NewRule[rules, $PDifNWellDifSamePotentialSpace, special, pDif, nWellDif, 0, "6.3.4"];
NewRule[rules, $NWellPDifSurround, surround, nWell, pDif, 5, "6.3.5"];
NewRule[rules, $NWellNWellDifSurround, surround, nWell, nWellDif, 3, "6.3.6"];
NewRule[rules, $NWellNDifSpace, interspace, nWell, nDif, 7, "6.3.7"];
NewRule[rules, $NWellDifNWellOverlap, overlap, nWellDif, nWell, 1, "6.3.8"];
NewRule[rules, $PWellDifNWellSpace, interspace, pWellDif, nWell, 5, "6.3.9"];
NewRule[rules, $PWellDifNWellDifSpace, interspace, nWellDif, pWellDif, 4, "6.3.10"];
NewRule[rules, $NDifPWellPDifNWellSpace, special, pDif, nDif, 12, "6.3.12"];
NewRule[rules, $NTransistorChannelExtension, extension, nDif, poly, 3, "6.3.18"];
NewRule[rules, $PTransistorChannelExtension, extension, pDif, poly, 3, "6.3.18"];
NewRule[rules, $PolyWidth, width, poly, NIL, 2, "6.4.1"];
NewRule[rules, $NTransistorChannelLength, special, nDif, poly, 2, "6.4.2"];
NewRule[rules, $PTransistorChannelLength, special, pDif, poly, 2, "6.4.2"];
NewRule[rules, $PolySpace, intraspace, poly, NIL, 25, "6.4.3", 10];
NewRule[rules, $NTransistorGateExtension, extension, poly, nDif, 2, "6.4.4"];
NewRule[rules, $PTransistorGateExtension, extension, poly, pDif, 2, "6.4.4"];
NewRule[rules, $PolyNDifSpace, interspace, poly, nDif, 1, "6.4.5"];
NewRule[rules, $PolyPDifSpace, interspace, poly, pDif, 1, "6.4.5"];
NewRule[rules, $PolyNWellDifSpace, interspace, poly, nWellDif, 1, "6.4.5"];
NewRule[rules, $PolyPWellDifSpace, interspace, poly, pWellDif, 1, "6.4.5"];
NewRule[rules, $ContactWidth, width, contact, NIL, 2, "6.5.1.1"];
NewRule[rules, $ContactMaxWidth, maxWidth, contact, NIL, 5, "6.5.1.2"];
NewRule[rules, $ContactSpace, intraspace, contact, NIL, 3, "6.5.1.3"];
NewRule[rules, $PolyContactSurround, surround, poly, contact, 1, "6.5.1.4"];
NewRule[rules, $PDifContactSurround, surround, pDif, contact, 1, "6.5.1.5"];
NewRule[rules, $PWellDifContactSurround, surround, pWellDif, contact, 1, "6.5.1.5"];
NewRule[rules, $NDifContactSurround, surround, nDif, contact, 1, "6.5.1.5"];
NewRule[rules, $NWellDifContactSurround, surround, nWellDif, contact, 1, "6.5.1.5"];
NewRule[rules, $ContactGateSpace, interspace, contact, gate, 15, "6.5.1.6", 10];
NewRule[rules, $PolyContactNDifSpace, interspace, contact, nDif, 2, "6.5.1.7"];
NewRule[rules, $PolyContactPDifSpace, interspace, contact, pDif, 2, "6.5.1.7"];
NewRule[rules, $PolyContactNWellDifSpace, interspace, contact, nWellDif, 2, "6.5.1.7"];
NewRule[rules, $PolyContactPWellDifSpace, interspace, contact, pWellDif, 2, "6.5.1.7"];
NewRule[rules, $Metal1ContactSurround, surround, metal1, contact, 1, "6.5.1.8"];
NewRule[rules, $NTransistorPWellDifSpace, interspace, pWellDif, gate, 3, "6.5.2.3"];
NewRule[rules, $PTransistorNWellDifSpace, interspace, nWellDif, gate, 3, "6.5.2.3"];

NewRule[rules, $MaxButSmaller, special, NIL, NIL, 5, "6.5.2.6"];
NewRule[rules, $MaxButLarger, special, NIL, NIL, 10, "6.5.2.6"];
NewRule[rules, $ButCutNDifOverlap, special, contact, nDif, 3, "6.5.2.7"];
NewRule[rules, $ButCutPDifOverlap, special, contact, pDif, 3, "6.5.2.7"];
NewRule[rules, $ButCutPWellContactOverlap, special, contact, pWellDif, 3, "6.5.2.7"];
NewRule[rules, $ButCutNWellContactOverlap, special, contact, nWellDif, 3, "6.5.2.7"];
NewRule[rules, $Metal1Width, width, metal1, NIL, 2, "6.6.1"];
NewRule[rules, $Metal1Space, intraspace, metal1, NIL, 3, "6.6.2"];
NewRule[rules, $DifViaSpace, special, NIL, NIL, 2, "6.7.11"];
NewRule[rules, $DifViaSurround, special, NIL, NIL, 2, "6.7.12"];
NewRule[rules, $ViaWidth, width, via, NIL, 2, "6.7.2"];
NewRule[rules, $ViaMaxWidth, maxWidth, via, NIL, 5, "6.7.3"];
NewRule[rules, $ViaSpace, intraspace, via, NIL, 4, "6.7.4"];
NewRule[rules, $Metal1ViaSurround, surround, metal1, via, 1, "6.7.5"];
NewRule[rules, $Metal2ViaSurround, surround, metal2, via, 1, "6.7.5"];
NewRule[rules, $PolyViaSpace, interspace, poly, via, 2, "6.7.6"];
NewRule[rules, $PolyViaSurround, surround, poly, via, 3, "6.7.7"];
NewRule[rules, $DifCutViaSpace, special, via, contact, 2, "6.7.8"];
NewRule[rules, $PolyCutViaSpace, interspace, via, contact, 3, "6.7.9"];
NewRule[rules, $Metal2Width, width, metal2, NIL, 3, "6.8.1"];
NewRule[rules, $Metal2Space, intraspace, metal2, NIL, 4, "6.8.2"];
NewMicronRule[rules, $PadMetalWidth, special, NIL, NIL, 127, "6.9.2"];
NewMicronRule[rules, $PadMetalViaSurround, special, NIL, NIL, 35, "6.9.3", 10];
NewMicronRule[rules, $Metal2PadSurround, surround, metal2, pad, 5, "6.9.4"];
NewMicronRule[rules, $PadMetalSpace, special, NIL, NIL, 51, "6.9.5"];
NewMicronRule[rules, $NWellMaxConnect, special, nWell, NIL, 75, "6.13.3.1"];
NewImplicitLayer[rules, pDif, nWell, FindRuleValue[rules, $NWellPDifSurround]];
NewImplicitLayer[rules, nWellDif, nWell, FindRuleValue[rules, $NWellNWellDifSurround]];
{
metal1Surround: RuleValue _ FindRuleValue[rules, $Metal1ContactSurround];
NewHoleType[rules, $PolyContact, metal1, poly, contact, metal1Surround, FindRuleValue[rules, $PolyContactSurround]];
NewHoleType[rules, $NDifContact, metal1, nDif, contact, metal1Surround, FindRuleValue[rules, $NDifContactSurround]];
NewHoleType[rules, $PDifContact, metal1, pDif, contact, metal1Surround, FindRuleValue[rules, $PDifContactSurround]];
NewHoleType[rules, $NWellDifContact, metal1, nWellDif, contact, metal1Surround, FindRuleValue[rules, $NWellDifContactSurround]];
NewHoleType[rules, $PWellDifContact, metal1, pWellDif, contact, metal1Surround, FindRuleValue[rules, $PWellDifContactSurround]];
};
NewHoleType[rules, $Via, metal1, metal2, via, FindRuleValue[rules, $Met1ViaSurround], FindRuleValue[rules, $Met2ViaSurround]];

NewMOSTransistorType[rules, $NTransistor, poly, nDif, NIL, FindRuleValue[rules, $NTransistorGateExtension], FindRuleValue[rules, $NTransistorChannelExtension], NIL];
NewMOSTransistorType[rules, $PTransistor, poly, pDif, nWell, FindRuleValue[rules, $PTransistorGateExtension], FindRuleValue[rules, $PTransistorChannelExtension], FindRuleValue[rules, $NWellPDifSurround]];

DesignRules.RegisterRuleSet[rules];

};

Generate[];

END.
-:VTIRulesImpl.mesa	
Copyright Ó 1987 by Xerox Corporation.  All rights reserved.
Barth, October 29, 1987 2:52:14 pm PST
gbb April 29, 1987 6:39:04 pm PDT
Last Edited by: Ross April 28, 1987 10:52:43 am PDT
This file comes from CMOS Lambda Layout Design Rules For Advanced Lithography, Greg Spadea, VTI Document 02-ECLA-2, Rev *F, January 10, 1987.  This rendition does not contain all sections of that document, nor are all sections represented here complete.  Should you require program access to a number from the VTI document DO NOT place it in your own code.  Contact the maintainer of this file and it will be added.
5.0 Drawn Layers
CPW, CR, CB, EXCL, TEXT, and DCTY layers are not used.
This file documents the single well process and so the p well is not drawn.
Tub resistors are not allowed.
N and P Diffusions are broken into diffusion which is intended to contact the well or substrate and that which is not.  Thus there are more layers than in the VTI document.  Use pDif or nDif when diffusion is not intended to contact well or substrate.  Use nWellDif or pWellDif when diffusion is intended to contact the well or substrate.
The butting layer is not drawn.  Butting contacts are special objects, as are transistors.
6.0 Generalized Layout Rules
6.1 Tub Rules
6.1.1 Min Width:
6.1.2 Min Space:
6.1.2.1 For tubs at same potential
6.1.2.2 For tubs at different potential (not greater than 5v)
6.1.3 Tubs are placed underneath all bonding pads with these exceptions and rules:
6.1.3.1 For the the N-Tub process no N-Tub under VSS pad.
6.1.3.2 For the P or Twin Tub process no P-Tub under VDD pad.
6.1.3.3 Tub overlap of metal 1 pad
6.1.4 Min P-Tub to N-Tub spacing
No P well defined in this file.
6.2 Tub Resistor Rules
Resistors are not allowed.
6.3 Diffusion Rules
6.3.1 Min Width 
$NDifWidth is used by ECAD as representing dif width
6.3.2 Min Transistor Width 
$NTransistorChannelWidth used by ECAD for xstor width
6.3.3 Min space between N+ to N+, P+ to P+, or P+ to N+ when the two adjacent diffusions are located on the same substrate and one or both are intended to be isolated from the substrate (such as a drain diffusion). 
$NDifSpace used by ECAD
Checking the next two rules requires knowing whether the nDif (pDif) is part of a butting contact or not.
6.3.4 Min space between N+ to P+ when the two adjacent diffusions are located on the same substrate and the diffusion of the opposite type of the substrate is at the same potential of the substrate (such as a source).
This is only used in butting contacts.
6.3.5 Min N- Tub overlap of a P+ diffusion when the P+ region is contained in the tub (such as a P-Channel source and drain).
6.3.6 Min N- Tub overlap of a N+ diffusion which is used for contacting the tub.
6.3.7 Min distance of N+ diffusion from the N- Tub edge when N+ is outside the tub (such as a N-Channel source and drain).
6.3.8 Min N+ guard ring overlap of N-Tub
The VTI rules distinguish between "blue" N+ diffusion used for contacting a tub and "blue" N+ diffusion used as a guard ring.  We currently have no way of encoding how "blue" N+ diffusion is used.  If we therefore say all "blue" N+ must be checked by both rules 6.3.6. and 6.3.8., then 6.3.8. is redundant.  That is, if a shape passes rule 6.3.6., it automatically passes rule 6.3.8.
Note that our name for blue N+ diffusion, nWellDif, seems to imply the use of contacting the nWell but not the use of being a guard ring.  As such, it may be a misnomer.
Louis feels that it would be OK if all uses of blue N+ were required to be surrounded by 3l of nWell.  VTI advises against using guard rings for internal circuits, and pad circuits may not be that area critical.
6.3.9 Min distance of a P+ diffusion used as P substrate contact from the edge of a N- Tub.
6.3.10 Min distance of a N+ guard ring of a N- Tub from a P+ diffusion contacting the substrate.
The "use" subtlety is lost.  See comments in section 6.3.8.
6.3.11 Min P- Tub overlap of a N+ diffusion when the N+ region is contained in the tub (such as a N-Channel source and drain).
No P well defined.
6.3.12 Min distance between a N+ diffusion contained in the P- tub and a P+ diffusion contained in the N- tub.  d5 + d7 or d11 + d13
This rule is redundant, with respect to either rules 6.3.5. and 6.3.7. or rules 6.3.11. and 6.3.14.  (Either nwell or pwell or both must be present.)
6.3.13 Min P- tub overlap of a P+ diffusion which is used for contacting the tub
No P well defined.
6.3.14 Min distance of a P+ diffusion from the P- tub edge when P+ is outside the tub (such as a P- channel source and drain).
No P well defined.
6.3.15 Min P+ guard ring overlap of the P- tub
No P well defined.
6.3.16 Min distance of a P+ guard ring of a P- tub from a N+ diffusion contacting the substrate.
Again, as in rule 6.3.10., the "use" subtlety is lost.  In fact, without this subtlety, this rule is identical to rule 6.3.10.
No P well defined.
6.3.17 Min distance of a N+ diffusion used as substrate contact from the edge of a P- Tub
No P well defined.
6.3.18 Minimum overlap of a P+ or N+ source/drain diffusion across a gate (in the direction of current flow.)
If this rule shrinks below 3 then 6.5.2.3 must be enforced. 
$NTransistorChannelExtension used by  ECAD for xstor channel extension
6.4 Polysilicon Rules
6.4.1 Min width
6.4.2 Min transistor length (5v max operation) 
NOT explicitly checked by ECAD
6.4.3 Min poly spacing
6.4.4 Min poly gate extension beyond diffusion over field oxide 
$NTransistorGateExtension used by ECAD
6.4.5 Min poly spacing to unrelated diffusion 
$PolyNDifSpace used by ECAD
Checking this rule by rectangle pairs requires that the errors between the gate poly and the channel diffusion be suppressed when a transistor is exploded.
6.5 Contact Rules
6.5.1 Contact to P+ And N+ Diffusion And Poly:
6.5.1.1 Min contact size
If this rule changes then 6.5.2.4 and 6.5.2.5 are affected.
6.5.1.2 Max contact size
Must know that the contact rectangle is not part of a butting contact.
6.5.1.3 Min contact to contact spacing
6.5.1.4 Min poly overlap of contact
Must know that contact rectangle belongs to poly contact.
6.5.1.5 Min diffusion overlap of contact 
$NDifContactSurround used by ECAD
Must know what sort of diffusion contact the contact rectangle belongs to.
6.5.1.6 Min contact to gate spacing
6.5.1.7 Min contact to poly spacing to diffusion 
$PolyContactNDifSpace used by ECAD
The subrules that pertain to nWellDif and pWellDif diffusion may be redundant:
1l	rule 6.4.5. poly avoids unrelated diffusion.
1l	rule 6.5.1.4. poly surrounds contact.
2l	TOTAL
The subrules that pertain to pDif and nDif are needed, in the event that the poly (at least 4l wide) that surrounds the contact extends over diffusion, making a transistor gate with length at least 4l.  (Otherwise, rule 6.4.5. would apply, as in the other cases mentioned above.)
Must know that the contact rectangle belongs to a poly contact.
6.5.1.8 Min metal 1 overlap of contact to poly and diffusion
If this rule changes then 6.5.2.8 is affected.
6.5.2 Contact To Butted P+ and N+ Diffusions (Butting Contact):
6.5.2.1 A butting contact is a single contact extending over a source and a substrate contact diffusion which are butted together.
6.5.2.2 The butting contact must be covered with the layer "butting" (CIF symbol CB) for proper design rule checking:
The butting layer is not defined.
6.5.2.3 Minimum distance between a poly edge over diffusion from opposite polarity diffusion.
This rule ensures that diffusion contacting the substrate or well stays away from gates.
ECAD uses $NTransistorPWellDifSpace.
6.5.2.4 Min butting contact width
This is the same as rule 6.5.1.1.  If it changes then 6.5.2.5 is affected.
6.5.2.5 Min butting contact size
Rule 6.5.3.7. requires a butting contact to overlap blue diffusion by at least 3l and to overlap green diffusion by at least 3l, for a total of 6l.  Rule 6.5.2.4. requires the minimum width to be 2l.  So this rule is redundant.
6.5.2.6 Maximum butting contact size
Checking this rule requires that the DRC know when a contact rectangle of any flavor is part of a butting contact.
6.5.2.7 Minimum extension of the contact into the source and substrate contact diffusion
Checking this rule requires that the DRC know when a contact rectangle of any diffusion flavor.
6.5.2.8 Minimum overlap of contact by metal 1
This is the same as 6.5.1.8.
6.6 Metal 1 Rules
6.6.1 Min width
6.6.2 Min space
6.6.3 Max current carrying capability 0.5 mA/m
6.7 Via Rules
6.7.1 A via can be placed over:
1) Diffusion.
VTI did not specify the diffusion surround via distance.  Accounting for mask misalignment we decided on 2.  The DRC must decide between the surround case and the space case.  We require that if the surround case applies that the designer use a single rectangle to perform the surround and that no other rectangles approach to within the space rule.  Because we do not wish via to appear over gate it must be the case that flattening a transistor does not produce diffusion rectangles which are the union of the source and drain but rather individual rectangles for each.
2) Poly over field oxide.
This is covered by rules 6.7.6 and 6.7.7
3) Field oxide
This is when nothing, other than n well, exists below the via and so no special rules are needed.
6.7.2 Min size
6.7.3 Max size
Except at the pads.
6.7.4 Min via to via space
6.7.5 Min metal 1 and 2 overlap of via
6.7.6 Min via to poly spacing
We might want to change this so that via over poly is always illegal.
Only when poly does not surround via, as for dif in 6.7.1.
6.7.7 Min poly overlap of via (when via is inside of the poly)
Need to know when poly surrounds, as for dif in 6.7.1.
6.7.8 Min via to contact of diffusion spacing
Need to know when dif/poly contact.  Not strictly true for this rule, unless you want to avoid making useless checks.  Any via and contact-to-poly which meet rule 6.7.9. (3l) automatically meet rule 6.7.8. (2l) too, even though the latter rule is inappropriate.
6.7.9 Min via to contact to poly spacing
This rule and 6.7.8 together define the spacing between via and contact. If this rule becomes smaller than 6.7.8 then 6.7.8 becomes interspace and this rule becomes special.
Need to know when dif/poly contact.  However, this rule is useful only if the via is on poly.  If the via is on field oxide or diffusion, rule 6.7.6. and rule 6.5.1.4. keep it at least 2 + 1 = 3l away from contact-to-poly.  So, if vias on poly were forbidden, this rule would be unnecessary.  See comments in section 6.7.7.
6.7.10 Max current carrying capability is 0.07 mA per micron of via hole periphery
6.8 Metal 2 Rules
6.8.1 Min width
6.8.2 Min space
6.8.3 Max current carrying capability 1.0 mA/m
6.9 Additional Layout Requirements (not shrinkable)
Most of the dimensions specified here are in microns.  When they are drawn on the layout grid the number of Lambda must be chosen in such a way that the final dimensions in microns are not smaller than the ones indicated (i.e. bond pad dimensions in microns are not shrinkable).
6.9.1 Bonding pads consist of a metal 1 pad, a via opening over metal 1, a metal 2 pad and opening into the passivation layers.
6.9.2 Minimum pad dimension for metal 1 & 2
6.9.3 Min metal 1 & 2 overlap of via
6.9.4 Min metal 2 overlap of pad mask (layer 70) opening
6.9.5 Min spacing between metal edges of adjacent pads
This is set to 51 instead of 50.8 so that the scaling is integer.
6.13 Layout Rules For CMOS I/O:
6.13.3 Internal Logic Layout Rules
6.13.3.1 Max tub connection space
Implicit Layers
Diffusion
Hole Types
Transistor Types
Registration
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