Test74LS163.tioga
Copyright Ó 1988 by Xerox Corporation. All rights reserved.
Barth, September 21, 1988 1:00:18 pm PDT
TimingGroups
Group  Format Delay Width Sample Threshold Levels
Clock  RZ   0  20  0    F  F;
Output NRZ  0  0  40    F  F;
Input  NRZ  10  0  0    F  F;
NameDutPinTimingGroup
Gnd    8  Input;
Vcc    16  Input;
nClear   1  Input;
EnableP   7  Input;
nLoad    9  Input;
EnableT   10  Input;
DataIn[0]   6  Input;
DataIn[1]   5  Input;
DataIn[2]   4  Input;
DataIn[3]   3  Input;
RippleCarryOut 15  Output;
DataOut[0]  14  Output;
DataOut[1]  13  Output;
DataOut[2]  12  Output;
DataOut[3]  11  Output;
Clock    2  Clock;
Include Dut16Fixture28.tioga
Include Fixture28.tioga
Include Vectors74LS163.tioga
End