DIRECTORY CD, CDCells, CDIO, Core, CoreClasses, CoreCreate, CoreOps, D2Orient, PWCore, Rope, RTBasic, RTTestUtil, TerminalIO; RTTestUtilImpl: CEDAR PROGRAM IMPORTS CDCells, CDIO, CoreClasses, CoreCreate, CoreOps, PWCore, RTBasic, TerminalIO EXPORTS RTTestUtil = BEGIN CreateInstance: PUBLIC PROC [actual: LIST OF Rope.ROPE, type: Core.CellType, name: Rope.ROPE, internalWires: Core.Wire, props: Core.Properties _ NIL] RETURNS [instance: CoreClasses.CellInstance] = { actualWire: Core.Wire _ BindWire[actual, internalWires]; instance _ CoreClasses.CreateInstance[actualWire, type, name, props]}; CreateRecordCell: PUBLIC PROC [name: Rope.ROPE, publicWires: Core.Wire, internalWires: Core.Wire _ NIL, instances: CoreClasses.CellInstances _ NIL, props: Core.Properties _ NIL, libDesign: CD.Design] RETURNS [cellType: Core.CellType] = { cellType _ CoreClasses.CreateRecordCell[publicWires, internalWires, instances, name, props]; IF libDesign # NIL THEN PWCore.SetGet[cellType, libDesign]}; CreateWire: PUBLIC PROC [ropeList: LIST OF Rope.ROPE] RETURNS [wire: Core.Wire] ~ { lowr: LIST OF CoreCreate.WR _ ConvertToWR[ropeList]; wire _ CoreCreate.WireList[lowr]}; AppendInstList: PUBLIC PROC [l1, l2: CoreClasses.CellInstances] RETURNS[val: CoreClasses.CellInstances] = { z: CoreClasses.CellInstances _ NIL; val _ l2; IF l1 = NIL THEN RETURN[val]; val _ CONS[l1.first, val]; z _ val; UNTIL (l1 _ l1.rest) = NIL DO z.rest _ CONS[l1.first, z.rest]; z _ z.rest; ENDLOOP; RETURN[val]; }; AppendRopeList: PUBLIC PROC [l1, l2: LIST OF Rope.ROPE] RETURNS[val: LIST OF Rope.ROPE] = { z: LIST OF Rope.ROPE _ NIL; val _ l2; IF l1 = NIL THEN RETURN[val]; val _ CONS[l1.first, val]; z _ val; UNTIL (l1 _ l1.rest) = NIL DO z.rest _ CONS[l1.first, z.rest]; z _ z.rest; ENDLOOP; RETURN[val]; }; WriteLayout: PUBLIC PROC [object: CD.Object, name: Rope.ROPE, design: CD.Design] = BEGIN [] _ CDCells.IncludeOb[design: design, cell: NIL, ob: object, trans: [off: [0, 0], orient: original], mode: doit]; IF ~CDIO.WriteDesign[design, name] THEN TerminalIO.PutRope["Error: design not written\n"]; END; BindWire: PROC [actual: LIST OF Rope.ROPE, internalWires: Core.Wire] RETURNS [actualWire: Core.Wire] = { reverseWireList: LIST OF CoreCreate.WR _ NIL; newWireList: LIST OF CoreCreate.WR _ NIL; FOR rl: LIST OF Rope.ROPE _ actual, rl.rest UNTIL rl=NIL DO r: Rope.ROPE _ rl.first; index: INT _ CoreOps.GetWireIndex[internalWires, r]; IF index < 0 THEN RTBasic.Error[callingError, NIL]; reverseWireList _ CONS[internalWires[index], reverseWireList]; ENDLOOP; FOR rl: LIST OF CoreCreate.WR _ reverseWireList, rl.rest UNTIL rl=NIL DO newWireList _ CONS[rl.first, newWireList]; ENDLOOP; actualWire _ CoreCreate.WireList[newWireList]; }; UnionWire: PUBLIC PROC [wire1, wire2: Core.Wire, name: Rope.ROPE _ NIL, props: Core.Properties _ NIL] RETURNS [union: Core.Wire] ~ { RETURN [CoreOps.UnionWire[wire1, wire2]]}; ConvertToWR: PROC [list: LIST OF Rope.ROPE] RETURNS[wrl: LIST OF CoreCreate.WR _ NIL] = { reverseWireList: LIST OF CoreCreate.WR _ NIL; UNTIL list = NIL DO reverseWireList _ CONS[list.first, reverseWireList]; list _ list.rest; ENDLOOP; UNTIL reverseWireList = NIL DO wrl _ CONS[reverseWireList.first, wrl]; reverseWireList _ reverseWireList.rest; ENDLOOP; RETURN[wrl]; }; -- of ConvertToWR END. pRTTestUtilImpl.mesa Copyright c 1985, 1986 by Xerox Corporation. All rights reserved. Bryan Preas, September 8, 1986 5:10:12 pm PDT create a cell instance rec create a cell instance rec Write a standard cell object to a CND design do wire binding by name Creates a new structured wire of size wire1.size+wire2.size, with corresponding name and properties Κγ˜šœ™Jšœ Οmœ7™BJšœ.™.—J˜šΟk ˜ Jšžœ žœb˜s—J˜šΟnœžœžœ˜Jšžœ žœ?˜TJšžœ ˜šž˜Icode˜—šŸœžœžœ žœžœžœ"žœ5žœžœ)˜ΖJ™J™Jšœ8˜8JšœF˜FJ˜—šŸœžœžœ žœ5žœ)žœžœ žœ žœ˜νJ™J™Kšœ\˜\Kšžœ žœžœ%˜Kšžœ˜—š žœžœžœ žœžœžœž˜HKšœžœ˜*Kšžœ˜—Jšœ.˜.Jšœ˜J˜—šŸ œžœžœ&žœžœžœžœ˜„Kšœc™cKšžœ$˜*K˜—šŸ œžœžœžœžœžœžœžœ žœžœ˜YKš œžœžœ žœžœ˜-šžœžœž˜Kšœžœ˜4K˜Kšžœ˜—šžœžœž˜Kšœžœ˜'Kšœ'˜'Kšžœ˜—Kšžœ˜ KšœΟc˜K˜—Jšžœ˜—J˜J˜J˜J˜—…— ζ9