TestRose.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Barth, January 5, 1988 12:18:59 pm PST
Jean-Marc Frailong January 25, 1988 11:12:06 am PST
DIRECTORY BitOps, Core, CoreClasses, CoreCreate, CoreFlat, CoreOps, Ports, Rosemary, RosemaryUser, RosemaryVector;
TestRose:
CEDAR
PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreOps, Ports, Rosemary, RosemaryUser, RosemaryVector
= BEGIN
CreateInverter:
PROC []
RETURNS [cellType: CoreCreate.CellType] = {
In: CoreCreate.Wire ← CoreOps.CreateWire[name: "In"];
Out: CoreCreate.Wire ← CoreOps.CreateWire[name: "Out"];
Gnd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Gnd"];
Vdd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Vdd"];
ntrans: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Out, Gnd]],
type: CoreClasses.CreateTransistor[nE]
]];
ptrans: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Out, Vdd, Vdd]],
type: CoreClasses.CreateTransistor[pE]
]];
cellType ← CoreClasses.CreateRecordCell[
public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
instances: LIST [ntrans, ptrans],
name: "Inverter"
];
};
Create2Inverter:
PROC []
RETURNS [cellType: CoreCreate.CellType] = {
In: CoreCreate.Wire ← CoreOps.CreateWire[name: "In"];
Out: CoreCreate.Wire ← CoreOps.CreateWire[name: "Out"];
Gnd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Gnd"];
Vdd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Vdd"];
Intern: CoreCreate.Wire ← CoreOps.CreateWire[name: "Intern"];
InInternOut: CoreCreate.Wire ← CoreCreate.WireList[LIST[In, Intern, Out], "InInternOut"];
inverter: CoreCreate.CellType ← CreateInverter[];
first: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Intern, Gnd, Vdd]],
type: inverter
]];
second: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [Intern, Out, Gnd, Vdd]],
type: inverter
]];
cellType ← CoreClasses.CreateRecordCell[
public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, Intern, InInternOut]],
instances: LIST [first, second],
name: "Inverter2"
];
};
in, out, gnd, vdd:
NAT ←
LAST[
NAT];
Test:
PROC = {
CheckIntern:
PROC [checkIntern:
BOOL, bit: Ports.Level] = {
IF checkIntern
THEN {
value: Ports.LevelSequence ← Rosemary.WireValue[sim, flatWire];
IF value.size#1 THEN ERROR;
IF value[0]#bit THEN ERROR;
};
};
SimpleTest:
PROC [checkIntern:
BOOL ←
FALSE] = {
p[in].l ← H;
Rosemary.Settle[sim];
IF p[out].l#H THEN ERROR;
CheckIntern[checkIntern, L];
p[in].l ← L;
Rosemary.Settle[sim];
IF p[out].l#L THEN ERROR;
CheckIntern[checkIntern, H];
};
cellType: CoreCreate.CellType ← Create2Inverter[];
p: Ports.Port ← NIL;
sim: Rosemary.Simulation ← NIL;
cutSet: CoreFlat.CutSet ← CoreFlat.CreateCutSet[cellTypes: LIST["Inverter2"]];
flatWire: CoreFlat.FlatWire ← NEW[CoreFlat.FlatWireRec ← CoreFlat.ParseWirePath[cellType, "Intern"]];
InitPorts[cellType.public];
[] ← Rosemary.SetFixedWire[cellType.public[vdd], H];
[] ← Rosemary.SetFixedWire[cellType.public[gnd], L];
[] ← Ports.InitPort[wire: cellType.public[in], levelType: l, initDrive: none];
[] ← Ports.InitTesterDrive[wire: cellType.public[in], initDrive: force];
[] ← Ports.InitPort[wire: cellType.public[out], levelType: l, initDrive: drive];
[] ← Ports.InitTesterDrive[wire: cellType.public[out], initDrive: none];
p ← Ports.CreatePort[cellType, TRUE];
sim ← Rosemary.Instantiate[cellType, p, cutSet];
SimpleTest[];
sim ← Rosemary.Instantiate[cellType, p];
SimpleTest[TRUE];
[] ← RosemaryUser.TestProcedureViewer[cellType, LIST["Inverter2Test"], "Inverter2Test", RosemaryUser.DisplayPortLeafWires[cellType]];
};
InitPorts:
PROC [public: CoreCreate.Wire] = {
in ← Ports.PortIndex[public, "In"];
out ← Ports.PortIndex[public, "Out"];
gnd ← Ports.PortIndex[public, "Gnd"];
vdd ← Ports.PortIndex[public, "Vdd"];
};
Inverter2Simple: Rosemary.EvalProc = {
p[out].l ← p[in].l;
};
Inverter2Test: RosemaryUser.TestProc = {
testPort: Ports.Port ← Ports.CreatePort[cellType];
target: RosemaryVector.Target ← NIL;
vector: RosemaryVector.VectorFile ← RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: testPort, read: FALSE];
flatCell: CoreFlat.FlatCellType ← NEW[CoreFlat.FlatCellTypeRec ← CoreFlat.ParseCellTypePath[cellType, "/0"]];
flatCellPublic: Core.Wire ← CoreFlat.ResolveFlatCellType[simulation.cellType, flatCell^].cellType.public;
target ← RosemaryVector.CreateTarget[simulation, flatCell, testPort];
InitPorts[cellType.public];
THROUGH [0..100)
DO
p[out].l ← p[in].l ← H;
Eval[];
RosemaryVector.SampleTarget[target, testPort];
RosemaryVector.WriteVector[vector];
p[out].l ← p[in].l ← L;
Eval[];
RosemaryVector.SampleTarget[target, testPort];
RosemaryVector.WriteVector[vector];
ENDLOOP;
RosemaryVector.CloseVectorFile[vector];
vector ← RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: testPort, read: TRUE];
THROUGH [0..100)
DO
p[out].l ← p[in].l ← H;
Eval[];
RosemaryVector.ReadVector[vector];
Ports.CheckPortValueEqual[flatCellPublic, p, testPort];
p[out].l ← p[in].l ← L;
Eval[];
RosemaryVector.ReadVector[vector];
Ports.CheckPortValueEqual[flatCellPublic, p, testPort];
ENDLOOP;
};
TestVector:
PROC = {
wire: CoreCreate.Wire ← CoreCreate.WireList[LIST["level", CoreCreate.Seq["levelSequence", 2], "bool", CoreCreate.Seq["boolSequence", 2], CoreCreate.Seq["cardinal", 2], CoreCreate.Seq["longCardinal", 2], CoreCreate.Seq["quadWord", 2]]];
cell: Core.CellType ← CoreClasses.CreateUnspecified[wire];
writePort, readPort: Ports.Port;
vector: RosemaryVector.VectorFile;
[] ← Ports.InitPort[wire[0], l];
[] ← Ports.InitPort[wire[1], ls];
[] ← Ports.InitPort[wire[2], b];
[] ← Ports.InitPort[wire[3], bs];
[] ← Ports.InitPort[wire[4], c];
[] ← Ports.InitPort[wire[5], lc];
[] ← Ports.InitPort[wire[6], q];
writePort ← Ports.CreatePort[cell];
writePort[0].d ← force;
writePort[0].l ← H;
writePort[1].d ← force;
FOR i:
NAT
IN [0..2)
DO
writePort[1].ls[i] ← H;
ENDLOOP;
writePort[2].d ← force;
writePort[2].b ← TRUE;
writePort[3].d ← force;
FOR i:
NAT
IN [0..2)
DO
writePort[3].bs[i] ← TRUE;
ENDLOOP;
writePort[4].d ← force;
writePort[4].c ← 1023;
writePort[5].d ← force;
writePort[5].lc ← 85;
writePort[6].d ← force;
writePort[6].q ← BitOps.BitQWordOnes;
vector ← RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: writePort, read: FALSE];
RosemaryVector.WriteVector[vector];
RosemaryVector.WriteVector[vector];
RosemaryVector.CloseVectorFile[vector];
readPort ← Ports.CreatePort[cell];
vector ← RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: readPort, read: TRUE];
RosemaryVector.ReadVector[vector];
Ports.CheckPortValue[wire, writePort, readPort];
RosemaryVector.ReadVector[vector];
Ports.CheckPortValue[wire, writePort, readPort];
};
[] ← Rosemary.Register[roseClassName: "Inverter2", evalSimple: Inverter2Simple];
RosemaryUser.RegisterTestProc["Inverter2Test", Inverter2Test];
END.