<> <> <> <> <<>> DIRECTORY BasicTime, Core, CoreClasses, CoreFlat, Ports, RefTab, Rope; Rosemary: CEDAR DEFINITIONS = BEGIN <> <> ROPE: TYPE = Core.ROPE; Stop: SIGNAL [msg: ROPE _ NIL, data: REF ANY _ NIL, reason: ATOM _ $Client]; <> <> BindCellType: PROC [cellType: Core.CellType, roseClassName: ROPE] RETURNS [sameCellType: Core.CellType]; BindCellClass: PROC [cellClass: Core.CellClass, roseClassName: ROPE] RETURNS [sameCellClass: Core.CellClass]; Register: PROC [roseClassName: ROPE, init: InitProc _ NIL, evalSimple: EvalProc _ NIL, copy: StateCopyProc _ NIL, scheduleIfClockEval: BOOL _ FALSE] RETURNS [sameRoseClassName: ROPE]; InitProc: TYPE = PROC [cellType: Core.CellType, p: Ports.Port, oldStateAny: REF ANY _ NIL, steady: BOOL _ FALSE] RETURNS [stateAny: REF ANY _ NIL, stateValue: Ports.LevelSequence _ NIL]; <> <<>> StateCopyProc: TYPE = PROC [from: REF ANY, to: REF ANY]; < 0 upon instantiation of a simulation which uses the celltype's EvalProc.>> <<>> EvalProc: TYPE = PROC [p: Ports.Port, stateAny: REF ANY, clockEval: BOOL] RETURNS [stateValue: Ports.LevelSequence _ NIL]; <> <> SetFixedWire: PROC [wire: Core.Wire, level: Ports.Level _ L] RETURNS [sameWire: Core.Wire]; <> SetWire: PROC [wire: Core.Wire, level: Ports.Level _ L, size: WireSize _ charge, memory: BOOL _ FALSE] RETURNS [sameWire: Core.Wire]; <> <<>> WireSize: TYPE = Ports.Drive[chargeWeak..chargeStrong]; SetTransistorCellTypeSize: PROC [transistor: Core.CellType, size: TransistorSize] RETURNS [sameTransistor: Core.CellType]; <> SetTransistorInstanceSize: PROC [transistor: CoreClasses.CellInstance, size: TransistorSize] RETURNS [sameTransistor: CoreClasses.CellInstance]; <<>> TransistorSize: TYPE = Ports.Drive[driveWeak..driveStrong]; Instantiate: PROC [cellType: Core.CellType, testPort: Ports.Port, cutSet: CoreFlat.CutSet _ NIL, statePoints: NAT _ 0] RETURNS [simulation: Simulation]; <> <> Initialize: PROC [simulation: Simulation, steady: BOOL _ TRUE, updateCellProc: UpdateCellProc _ NIL]; <> <<>> SettleToTest: PROC [simulation: Simulation, flatCell: CoreFlat.FlatCellType, test: Ports.Port]; <> Settle: PROC [simulation: Simulation, updateProc: UpdateProc _ NIL, memory: BOOL _ TRUE, clockEval: BOOL _ FALSE, updateCellProc: UpdateCellProc _ NIL]; UpdateProc: TYPE = PROC [roseWire: RoseWire]; UpdateCellProc: TYPE = PROC [roseInstance: RoseCellInstance, stateValue: Ports.LevelSequence]; <> <<>> <> NotInstantiated: SIGNAL; <> <<>> GetFlatWire: PROC [roseWire: RoseWire] RETURNS [flatWire: CoreFlat.FlatWireRec]; <> <<>> WireValue: PROC [simulation: Simulation, flatWire: CoreFlat.FlatWire] RETURNS [value: Ports.LevelSequence]; <> GetValues: PROC [simulation: Simulation, flatWire: CoreFlat.FlatWire] RETURNS [values: RoseValues]; <> GetState: PROC [simulation: Simulation, flatCell: CoreFlat.FlatCellType] RETURNS [stateAny: REF ANY]; <> <<>> StatePoint: PROC [simulation: Simulation, point: NAT]; <> RestoreState: PROC [simulation: Simulation, point: NAT]; <> <> PrintPeriod: PROC [prefix: Rope.ROPE, from, to: BasicTime.GMT]; <> <> <<>> <> <> <> < 16 words/transistor>> < 32 words/wire + quantization of RoseTransistorSeq>> <> <<>> RoseCellType: TYPE = REF RoseCellTypeRec; RoseCellTypeRec: TYPE = RECORD [ evalSimple: EvalProc _ NIL, init: InitProc _ NIL, copy: StateCopyProc _ NIL, scheduleIfClockEval: BOOL _ FALSE]; Simulation: TYPE = REF SimulationRec; SimulationRec: PUBLIC TYPE = RECORD [ cellType: Core.CellType _ NIL, coreToRoseWires: RefTab.Ref _ NIL, coreToRoseInstances: RefTab.Ref _ NIL, coreToRoseValues: RefTab.Ref _ NIL, instanceNeedEval: RoseCellInstance _ NIL, instanceNeedEvalWhenNotClockEval: RoseCellInstance _ NIL, perturbed: RoseWire _ NIL, roseBoolWires: RoseWireList _ NIL, publicBindings: PortBindings _ NIL, scratchValue: Ports.LevelSequence _ NIL, scratchDrive: Ports.DriveSequence _ NIL, vicinityByStrength: ARRAY Ports.Drive OF VicinityRec, testPort: Ports.Port _ NIL, statePoints: PortSequence _ NIL, mosSimTime: INT _ 0]; VicinityRec: TYPE = RECORD[ wires: RoseWires, firstFree: CARDINAL _ 0]; PortSequence: TYPE = REF PortSequenceRec; PortSequenceRec: TYPE = RECORD [ports: SEQUENCE size: NAT OF Ports.Port]; RoseCellInstance: TYPE = REF RoseCellInstanceRec; RoseCellInstanceRec: TYPE = RECORD [ nextNeedEval: RoseCellInstance _ NIL, nextNeedEvalWhenNotClockEval: RoseCellInstance _ NIL, roseCellType: RoseCellType _ NIL, publicPort: Ports.Port _ NIL, portBindings: PortBindings _ NIL, state: REF ANY _ NIL, statePoints: SRA _ NIL, instance: CoreFlat.FlatCellTypeRec, data: REF ANY _ NIL]; SRA: TYPE = REF SRASeq; SRASeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF REF ANY]; PortBindings: TYPE = REF PortBindingSeq; PortBindingSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF PortBinding]; PortBinding: TYPE = REF PortBindingRec; PortBindingRec: TYPE = RECORD [ instance: RoseCellInstance _ NIL, clientPort: Ports.Port _ NIL, fields: Fields _ NIL, currentDrive: Ports.Drive _ none, statePoints: Ports.DriveSequence _ NIL]; DriveSequenceSequence: TYPE = REF DriveSequenceSequenceRec; DriveSequenceSequenceRec: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF Ports.DriveSequence]; Fields: TYPE = REF FieldSeq; FieldSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF Field]; Field: TYPE = REF FieldRec; FieldRec: TYPE = RECORD [ portBinding: PortBinding _ NIL, portStartBit: NAT _ 0, roseWire: RoseWire _ NIL, currentDrive: Ports.DriveSequence _ NIL, currentValue: Ports.LevelSequence _ NIL, driveStatePoints: DriveSequenceSequence _ NIL, valueStatePoints: LevelSequenceSeq _ NIL]; RoseWireList: TYPE = LIST OF RoseWire; RoseWires: TYPE = REF RoseWireSeq; RoseWireSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF RoseWire]; RoseWire: TYPE = REF RoseWireRec; RoseWireRec: TYPE = RECORD [ firstFreeConnection: CARDINAL _ 0, connections: Fields _ NIL, currentValue: Ports.LevelSequence _ NIL, < The wire is atomic. The following fields are only significant if the wire is atomic.>> nextPerturbedWire: RoseWire _ NIL, previousPerturbedWire: RoseWire _ NIL, nextRecomputed: RoseWire _ NIL, nextVicinityWire: RoseWire _ NIL, channels: RoseTransistors _ NIL, notOffChannels: RoseTransistors _ NIL, validNotOffChannels: CARDINAL _ 0, gates: RoseTransistors _ NIL, switchDrive: Ports.Drive _ none, upDrive: Ports.Drive _ none, downDrive: Ports.Drive _ none, wireDrive: Ports.Drive _ charge, connectionDrive: Ports.Drive _ none, connectionLevel: Ports.Level _ L, wireLevel: Ports.Level _ L, mark: BOOL _ FALSE, memory: BOOL _ FALSE, statePoints: REF ANY _ NIL, -- TypeUnion[Ports.LevelSequence, LevelSequenceSeq] data: REF ANY _ NIL, -- Normally used by RosemaryUser for plotting wire: CoreFlat.FlatWireRec]; LevelSequenceSeq: TYPE = REF LevelSequenceSeqRec; LevelSequenceSeqRec: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF Ports.LevelSequence]; RoseValues: TYPE = LIST OF RoseValue; RoseValue: TYPE = RECORD [ roseWire: RoseWire _ NIL, fieldStart: NAT _ 0, fieldWidth: NAT _ 0]; <<>> RoseWireData: TYPE = REF RoseWireDataRec; RoseWireDataRec: TYPE = RECORD [value: Ports.Level, size: Ports.Drive, memory: BOOL]; RoseTransistors: TYPE = REF RoseTransistorSeq; RoseTransistorSeq: TYPE = RECORD [elements: SEQUENCE size: CARDINAL OF RoseTransistor]; RoseTransistor: TYPE = REF RoseTransistorRec; RoseTransistorRec: TYPE = RECORD [ gate: RoseWire _ NIL, ch1: RoseWire _ NIL, ch2: RoseWire _ NIL, conductivity: Ports.Drive _ drive, type: CoreClasses.TransistorType _ nE, instance: CoreFlat.FlatCellTypeRec]; END.