Check should check that wires with strength force have the values they ought.

Keep a list of what changed on RoseCellInstance, hand it to eval proc and nil it out. Short cuts loops in address decoders.

Enhance RAM model at array level to assume one hot and use ref sequence of bits for data and just jam data out with strength drive.

Allow client to supply init and eval for public or internal, supply dummies if he doesn't => instance never nil

Put a wireStartBit in FieldRec. Allows taking a subfield of a RoseWire. Optimization for picking single bit out of a bus. How should this optimization be detected during instantiation?

Abstraction by behavioural primitives specifying a manipuable form so that the simulator can statically combine the functions. Form could be boolean equasions ala Alps or a new switching algebra along the lines of what is needed for static analysis, i.e. what is channel connected to what or what MOSSIM uses. Write a little piece of microcode that evaluates this normal form.

Add generator and eval proc for Alps.

Drivers.mesa instead of ValueWires.mesa?

Have instantiate take stats: Core.STREAM, not NIL prints out static statistics.

Have behavioural procs tell simulator what changed.

Eliminate input only from writers (doesn't help much if writers are sorted and none is not checked).

Eliminate output only from readers (may not help much because one writer for multiple readers normally).

If single writer, any readers, always driven and access sequence=storage sequence in type as well as bits then value wire ref of writer and readers as well as field refs of writer and readers all point to same sequence. Not rose wire ref, need original value to determine if it changed. Think about necessity for always driven.

If all value wire fields were refs this gimic could be played at a low level, even for b, c, lc. Requires no eval proc syntax change.

If no LXH connection to RoseWire then store value as sequence of Bools instead of Levels (only if one writer, multiple writers may need to result in X's, or special case the X's).

Since fields always apply to whole wires can keep the writers sorted by strength so that copying into scratch not needed and array of strengths of writer rings can be kept to speed up computing new value. Maybe just keep connections sorted by writer strength and forget the array of rings stuff.

Keep track of maximum vicinities and mark them as having no gates with X on them and then use the single pass algorithm that used to be in Rosemary to compute those vicinities. Should result in a factor of 3 speedup.

Put marks on the core public wire to indicate where the behaviour proc is accessing the values. Makes it less likely that it is changed on the fly. Allows some optimizations that would otherwise not be possible. The allocation of the value wire can cut off at the level at which the behaviour proc extracts and inserts values.

Allow composites of L, H, and X by adding another parallel bit vector which masks the bits which are X.

Put another field in the value wire that allows arbitrary size bit vectors.

Don't use properties during instantiation, use reftabs.

Eliminate init and eval from instantiate, causes whole internal to be examined after every Eval.

Put cheap transistors in. Change CoreFlatten to directly create the Rosemary data structure. Figure out how to compute which instance the designer is talking about when referring to hierarchical structure, also back the other way. Perhaps forget all this nonsense for first implementation.

Move bits into readers when val changes, not when reader is scheduled.

Allow internal nodes to have more than one bit, if any are X then all are X. Change reader handler to look at collections of bits.

Keep list sideways through value tree of place where designer is accessing. Use for shuffling bits.

Change Fields and ValueWireBindings in RosemaryImpl into sequences to speed access through locality and eliminating memory references.

Keep transistors which are on sorted into beginning of RoseWireRec.channels, need not consider those that are off during value computation.

One hot array structures run proportional to N**2 if they are N on a side. Keep a list of potentially on transistors, i.e. gate#L, so that not all transistors attached to a wire need be considered every time. This should speed up RAM simulations by O(N).