<> <> <> <> <> <> <> <<>> DIRECTORY Core, CoreClasses, CoreFlat, CoreOps, Commander, IO, ProcessProps, Rosemary; RoseDebug: CEDAR PROGRAM IMPORTS CoreFlat, CoreOps, IO, ProcessProps EXPORTS = BEGIN OPEN Rosemary; HackSignal: SIGNAL = CODE; CorrespondingPublic: PUBLIC PROC [instance: CoreClasses.CellInstance, actual: Core.Wire] RETURNS [public: Core.Wire _ NIL] = { EachWirePair: CoreOps.EachWirePairProc = { IF actualWire=actual THEN {public _ publicWire; quit _ TRUE}; }; [] _ CoreOps.VisitBinding[instance.actual, instance.type.public, EachWirePair]; }; <<_ RoseDebug.FindHack[&new.data[0].type.data[49].type, &new.data[0].type.data[49].type.data.internal[11590]]>> FindHack: PROC [cellType: Core.CellType, wire: Core.Wire] = { rct: CoreClasses.RecordCellType _ NARROW[cellType.data]; FOR i: NAT IN [0..rct.size) DO IF CoreOps.RecursiveMember[rct[i].actual, wire] THEN { subrct: CoreClasses.RecordCellType _ NARROW[rct[i].type.data]; subWire: Core.Wire _ CorrespondingPublic[rct[i], wire]; FOR j: NAT IN [0..subrct.size) DO IF CoreOps.RecursiveMember[subrct[j].actual, subWire] THEN GOTO found; REPEAT found => { CoreOps.Print[rct[i].type]; SIGNAL HackSignal[]; }; ENDLOOP; }; ENDLOOP; }; <> <> <1000 THEN SIGNAL HackSignal;>> <<};>> <> <<};>> <<>> <> <> <> <1000 THEN SIGNAL HackSignal;>> <<};>> <<[] _ HashTable.Pairs[table: simulation.coreToRoseWires, action: FindWire];>> <<};>> <<>> <> <> <> <> <> <> <> <> <> <> <> <> <> <<};>> <> <<};>> <<>> <> <> <> <> <> <> <> <> <<};>> <<>> <> <<>> <> <> <> <<};>> <<>> <<[] _ HashTable.Pairs[table: simulation.coreToRoseWires, action: ConsWires];>> <<};>> <<>> <> <<>> <> <> <> <> <> <<};>> <<>> <<[] _ HashTable.Pairs[table: simulation.coreToRoseWires, action: CountConnections];>> <> <<};>> <<>> FilterXWires: PROC [sourceWires: LIST OF RoseWire] RETURNS [xwires: LIST OF RoseWire _ NIL] = { FOR roseWires: LIST OF RoseWire _ sourceWires, roseWires.rest UNTIL roseWires=NIL DO roseWire: RoseWire _ roseWires.first; IF roseWire.currentValue=NIL THEN { IF roseWire.wireLevel=X THEN xwires _ CONS[roseWires.first, xwires]; } ELSE FOR bit: CARDINAL IN [0..roseWire.currentValue.size) DO IF roseWire.currentValue[bit]=X THEN xwires _ CONS[roseWires.first, xwires]; ENDLOOP; ENDLOOP; }; <> <<>> <> <> <> <<};>> <<>> <<[] _ HashTable.Pairs[table: simulation.coreToRoseWires, action: ConsWires];>> <<};>> <<>> <> <> <> <> <> <> <<};>> <<>> PrintRecompute: PROC [simulation: Simulation, recomputed: RoseWire, out: Core.STREAM _ NIL] = { IF out=NIL THEN out _ NARROW [ProcessProps.GetProp[$CommanderHandle], Commander.Handle].out; FOR recomputed _ recomputed, recomputed.nextRecomputed UNTIL recomputed=NIL DO IO.PutRope[out, CoreFlat.WirePathRope[simulation.cellType, recomputed.wire]]; IO.PutRope[out, "\n"]; ENDLOOP; }; <> <> <> <> <> <> <> <> <> <<};>> <<>> <> <<>> <> <> < "e",>> < "n",>> < "cw",>> < "cmw",>> < "c",>> < "cms",>> < "cs",>> < "f",>> < "dw",>> < "dmw",>> < "d",>> < "dms",>> < "ds",>> < "i",>> < ERROR]];>> <<};>> <<>> <> <> < "L",>> < "H",>> < "X",>> < ERROR]];>> <<};>> <<>> <> < "n", pE => "p", nD => "d", ENDCASE => ERROR], Drive[trans.conductivity]];>> <<};>> <<>> <> <> <> <> <<[] _ HashTable.Insert[table: tranTab, key: trans[t], value: $Transistor];>> <> <<};>> <<>> <> <> <> <> <> <<};>> <> <> <> <> <<};>> <<>> <> <> <> <> <> < -"];>> <> <> <<};>> <<>> <> <> <> <> <> <> <> <> <> <> <> <<}>> <> <> <<};>> <> <<};>> <<>> <> <> <> <<[] _ HashTable.Pairs[table: simulation.coreToRoseWires, action: PrintWires];>> <<[] _ HashTable.Pairs[tranTab, PrintEachTransistor];>> <<};>> <<>> END.