PWCoreLichen.mesa
Copyright Ó 1986, 1987 by Xerox Corporation. All rights reversed.
Created by Bertrand Serlet, July 14, 1986 5:49:00 pm PDT
Bertrand Serlet, April 2, 1987 11:31:33 pm PST
Mike Spreitzer March 4, 1987 11:39:39 am PST
Last tweaked by Mike Spreitzer on September 27, 1988 12:04:34 pm PDT
Louis Monier March 30, 1988 11:58:43 am PST
DIRECTORY CD, Core, CoreFlat, CoreStructuralComparison, OneToOne, RefTab, SymTab;
PWCoreLichen: CEDAR DEFINITIONS = BEGIN
Purpose
This interface defines how do the comparison between the source Core data structure, and the extracted Core data structure. The comparison is done hierarchically. Places where layout has been explicitly associated to the Core data structure are places where source and extracted structures are known to match (or at least should match). The comparison process also decorates both structures with the mapping that maps one into the other.
Basics
CellType: TYPE = Core.CellType;
Wire: TYPE = Core.Wire;
ROPE: TYPE = Core.ROPE;
Properties: TYPE = Core.Properties;
Wires: TYPE = Core.Wires;
TransistorTolerances: TYPE = CoreStructuralComparison.TransistorTolerances;
The comparison
Compare: PROC [root: CellType, context: Context, ttols: TransistorTolerances ← wideTransistorTolerances] RETURNS [allOK: BOOL];
Layout must be attached to this root CellType.
This function calls itself recursively for cellTypes such that PWCore.GetLayoutAtom[cellType]#NIL.
If there is a process property $AbortBool that is a REF BOOL, it is sampled now & then to decide whether to abort.
Not allOK if any subtree had mismatch.
CompareForTheRestOfUs: PROC [root: CellType, design: CD.Design, precision: REAL ← 0.90] RETURNS [allOK: BOOL];
Same as above, but easier to call from the interpreter
design must be specified: it is the source design
precision=1 => perfect match; precision=0 => don't care; default is 90%
Context: TYPE ~ RECORD [
design: CD.Design,
root: CellType ← NIL,
path: CoreFlat.FlatCellTypeRec ← CoreFlat.rootCellType
];
wideTransistorTolerances: READONLY TransistorTolerances;
tightTransistorTolerances: READONLY TransistorTolerances;
TolerancesSpec: TYPE ~ RECORD [length, width: REAL ← 0.0];
Each field > 0 specifies a ratio. We're not being careful about what's in the numerator vs. what's in the denominator.
transistorTolerancesProp: READONLY ATOM --$LichenTransistorTolerances--;
On any source cell type with layout attached, you may give this property a value that is a ROPE. Rope.Cat["[", that value, "]"] should evaluate (via the interpreter) to a TolerancesSpec. A field > 0 specifies the tolerance used `below' that point. Actually that's a bit of a lie --- the tolerances used in a subtree are determined by some path from the root --- no guarantees about which path.
RefineTolerances: PROC [propval: REF ANY, inherit: TransistorTolerances] RETURNS [TransistorTolerances];
FormatTolerances: PROC [TransistorTolerances] RETURNS [ROPE];
BadRoot: SIGNAL [root: CellType];
Raised if you call Compare on a cell that can't serve as a root (i.e., no recast of it has a layout atom, at the time this interface was last edited). RESUMEing simply assumes the comparison would succeed.
Message: SIGNAL [msg: ROPE];
Raised by Compare to give the user a chance to examine brokenness.
FoundProblems: SIGNAL [source, extracted: CellType];
Raised by Compare to: (a) signal user that he's seen all the problem with this pair, and (b) inform client that this pair had problems.
ForgetComparisons: PROC [root: CellType];
The fact that a subtree has been compared is remembered. Call this procedure to forget such facts. Call it only on a subtree root (i.e., a cell type with a PWCore layout attachment).
GlobalForget: PROC;
Forget comparison results everywhere.
SetAutomorphismHack: PROC [enabled: BOOL];
When the automorphism hack is enabled, when the graph isomorphism gets stuck, it will try to push on by making a random association from a potential automorphism. Since there is no backtracking, this doesn't make a proper graph isomorphism algorithm --- this can give false negatives.
GetAutomorphismHack: PROC RETURNS [enabled: BOOL];
SetQuitEarly: PROC [may: BOOL];
GetQuitEarly: PROC RETURNS [may: BOOL];
DisplayStats: PROC;
trace: SymTab.Ref;
GetConstraints: PROC [subroot: CellType] RETURNS [RefTab.Ref];
Every value is another RefTab.Ref representing a constraint; every key of that inner RefTab.Ref is a public atomic wire of subroot. Outer table is NIL when no constraints.
END.