<> <> <> <> DIRECTORY Core, CoreClasses, CoreFlat, DABasics, Pipal, PipalInt, PipalMos, RefTab; PipalCore: CEDAR DEFINITIONS IMPORTS Pipal = BEGIN <> <> <> <> <> <> Decoration: TYPE = REF DecorationRec; <> <> <<>> <> DecorationRec: TYPE = PRIVATE RECORD [ name: Core.ROPE, -- Documentation purpose only portProp: ATOM, -- Hangs on each public wire to specify the ports of the public. Ports should be understood as the more general meaning of "interface geometry". objectProp: ATOM, -- Hangs on some cellTypes to specify the corresponding object. Currently only cellTypes of the recordCellClass and transistors have this decoration. geometryProp: ATOM, -- Hangs on every internal wires of record cellTypes to specify the geometry of the internal (but only at this level in the record). transProp: ATOM -- hangs on every CoreClasses.CellInstance of record cellTypes to specify the corresponding transformation. ]; layoutDecoration: Decoration; schematicsDecoration: Decoration; rawLayoutDecoration: Decoration; CreateDecoration: PROC [name: Core.ROPE, coreSave: BOOL _ FALSE] RETURNS [decoration: Decoration]; <> <> <> <> <> <<>> HasPort: PROC [decoration: Decoration, public: Core.Wire] RETURNS [BOOL]; <> GetPort: PROC [decoration: Decoration, public: Core.Wire] RETURNS [port: Pipal.Object _ Pipal.void]; <<>> PutPort: PROC [decoration: Decoration, public: Core.Wire, port: Pipal.Object]; <> <<>> AddPort: PROC [decoration: Decoration, public: Core.Wire, port: Pipal.Object]; <> <> <<>> PutClippedPort: PROC [decoration: Decoration, public: Core.Wire, abutBox: PipalInt.Rectangle, subPort: Pipal.Object]; <> <<>> PutRecordPorts: PROC [decoration: Decoration, record: Core.CellType, abutBox: PipalInt.Rectangle]; <> <> <<>> <