[_CD4_]<datools7.0>NewSC25>SC.mesa!2

SC.mesa

Last Edited by: Preas, August 24, 1987 3:43:20 pm PDT

Jean-Marc Frailong October 14, 1987 5:58:52 pm PDT

DIRECTORY

CD, Core, DABasics, Rope, Route, RTCoreUtil;

SC: CEDAR DEFINITIONS = BEGIN

Theory

This interface defines the basic data structures and procedures to define a standard cell object from a Core description.

Common Types

RopeList: TYPE = LIST OF Rope.ROPE;

Layer: TYPE = CD.Layer;

Rect: TYPE = CD.Rect;

RefRect: TYPE = REF Rect;

Pos: TYPE = CD.Position;

Number: TYPE = CD.Number;

SideOrNone: TYPE = DABasics.SideOrNone;

Side: TYPE = DABasics.Side;

Direction: TYPE = DABasics.Direction;

Errors

Error: ERROR [errorType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];

Signal: SIGNAL [signalType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];

ErrorType: TYPE = {programmingError, callingError, noResource, other};

Design Rules

DesignRules: TYPE = REF DesignRulesRec;

DesignRulesRec: TYPE = RECORD[

horizLayer, vertLayer: Rope.ROPE,

rowParms, sideParms: Route.DesignRulesParameters,

rowRules, sideRules: Route.DesignRules

];

CreateDesignRules: PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: Direction] RETURNS [designRules: DesignRules];

Define the standard cell design rules. technologyKey values must correspond to one of the ChipNDale technologies. horizLayer, vertLayer should be "poly", "metal" or "metal2".

Standard Cell Handles and Results

Handle: TYPE = REF HandleRec;

HandleRec: TYPE = RECORD [

name: Rope.ROPE ← NIL,

coreCellType: Core.CellType ← NIL,

rules: DesignRules ← NIL,

parms: PRIVATE REF ANY ← NIL,

structureData: PRIVATE REF ANY ← NIL,

layoutData: PRIVATE REF ANY ← NIL];

Result: TYPE = REF ResultRec;

ResultRec: TYPE = RECORD[

handle: Handle,

object: CD.Object,

rect: Rect ← [0, 0, 0, 0],

polyLength, metalLength, metal2Length, polyToMetal, metalToMetal2: NAT ← 0,

numIncompletes: NAT ← 0,

incompleteNets: RopeList ← NIL,

stats: LIST OF ChannelStats ← NIL]; -- detailed stastics for evaluation; not rerurned in production mode

ChannelStats: TYPE = REF ChannelStatsRec;

ChannelStatsRec: TYPE = RECORD[

channel: INT ← 0,

netStats: LIST OF NetEntry ← NIL];

NetEntry: TYPE = REF NetEntryRec;

NetEntryRec: TYPE = RECORD[

name: Rope.ROPE ← NIL,

leftExit, rightExit: BOOL ← FALSE,

pinStats: LIST OF PinEntry ← NIL,

ftStats: LIST OF PinEntry ← NIL];

PinEntry: TYPE = REF PinEntryRec;

PinEntryRec: TYPE = RECORD[

bottom: BOOL ← FALSE,

position: INT ← 0];

CreateHandle: PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE ← NIL, designRules: DesignRules, name: Rope.ROPE ← NIL] RETURNS [handle: Handle];

Create a StdCellHandle. The StdCellHandle definition includes the design rules (conductor and via widths and spacings) for the routing channels as well as the circuit structure definition.

Properties

row and logic cell properties

numRows: ATOM;

Used to specify the number of rows for a standard cell assembly. Should be a property on Core cellType being laid out

rowProp: ATOM;

Used to specify the row on which a logic cell is to be placed. rowProp and and INT row number should be a property/value on a logic cell insatance

positionProp: ATOM;

Used to specify the position of a logic within a row or of an public pin on a side. Should be used with INT value on logic cell instance.

side and public properties

bottomSideProp, rightSideProp, topSideProp, leftSideProp: ATOM;

Used to specify the side on which a public pin is to be placed. (mumble)SideProp should be a TRUE on a public wire if it is to appear on (mumble) side

bottomPositionProp, rightPositionProp, topPositionProp, leftPositionProp: ATOM;

Used to specify the position (INT) in which a public pin is to be placed on a side. (mumble)SideProp must be true on that side; should be a property/value on a public wire

usePublicPositionsProp: ATOM;

Used to specify the position of a public in the schematic is to be retained int the layout; value must be TRUE

bottomMaxExits, rightMaxExits, topMaxExits, leftMaxExits: ATOM;

Used to specify the maximum number or exits on a side.

bottomExitSpacing, rightExitSpacing, topExitSpacing, leftExitSpacing: ATOM;

Used to specify the HINT for publics spacing on a side.

placement properties

investmentProp, veryLongValue, longValue, mediumValue, shortValue, veryShortValue: ATOM;

Used to specify indirectly the investment to make in placement.

t0SA, maxTStepSA, lambdaSA, tableSizeSA, limitSA: ATOM;

Used to specify DIRECTLY the investment to make in placement.

interestingProperties: RTCoreUtil.PropertyKeys;

Used to specify all the properties that aer interesting to SC

widthFactorProp: ATOM;

specifies the allowed length of the longest row compared to the minimun distance longest row

internal use

handleAtom: ATOM;

for internal use only

Standard Cell Optimization and Construction

The following operations are available for a standard cell design.

InitialPlace: PROC [handle: Handle, numRows: NAT ← 0];

Determine an initial placement for the instances.

PosImprove: PROC [handle: Handle, maxCycles: INT ← 5];

Improve the positions of instances within rows.

FTImprove: PROC [handle: Handle, maxCycles: INT ← 5];

Improve the positions of the feedthrus within rows.

PosImproveWL: PROC [handle: Handle, maxCycles: INT ← 5];

Improve the positions of instances within rows using wire lenght as figure of merit.

OrientImprove: PROC [handle: Handle, maxCycles: INT ← 5];

Improve the orientation of instances.

OrientImproveWL: PROC [handle: Handle, maxCycles: INT ← 5];

Improve the orientation of instances using wire lenght as figure of merit.

HowLongToWork: TYPE = {veryLong, long, medium, short, veryShort, noInvestmentProp};

SAParms: TYPE = RECORD [

t0: REAL ← 100000.0, maxTStep: REAL ← 0.75, lambda: REAL ← 0.7, tableSize, limit: INT ← 200];

SAInitialResult: TYPE = RECORD [

minScore, maxScore, minDelta, maxDelta, avgDelta, standardDeviation: REAL ← 0.0,

numTotal, numDecrease, numIncrease, numNeutral: INT ← 0];

SAInitialPlace: PROC [handle: Handle, widthFactor: REAL ← 1.1, seed: INT ← 0] RETURNS [initialResult: SAInitialResult];

Initialize for simulated annealing improvement.

SAGetParms: PROC [handle: Handle, initialResult: SAInitialResult, cellType: Core.CellType] RETURNS [saParms: SAParms];

determine parameters for simulated placement.

SAPlaceImprove: PROC [handle: Handle, saParms: SAParms, widthFactor: REAL ← 1.1, seed: INT ← 0];

Improve the placement for the instances (in pairs) by simulated annealing.

SAPlaceImproveM: PROC [handle: Handle, saParms: SAParms, widthFactor: REAL ← 1.1, seed: INT ← 0];

Improve the placement for the instances (one at a time) by simulated annealing.

PlaceImprove: PROC [handle: Handle, maxCycles: INT ← 0];

Improve the placement for the instances by exhaustive search.

GlobalRoute: PROC [handle: Handle];

Determine strategic paths for the wiring that must cross cell rows.

ExprGlobalRoute: PROC [handle: Handle];

Determine strategic paths for the wiring that must cross cell rows. Uses experimental global routing

DetailRoute: PROC [handle: Handle] RETURNS [result: Result];

Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object.

ExprDetailRoute: PROC [handle: Handle] RETURNS [result: Result];

Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object. Uses experimental global routing

StandardCellPlaceTW: PROC [cellType: Core.CellType];

send a placement ot Timberwolf for placement

Clean Up

Destroy: PROC [handle: Handle];

Remove circular references so garbage collection can work

Sugar

CreateLayout: PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: Direction, numRows: NAT, cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE ← NIL, name: Rope.ROPE ← NIL] RETURNS [object: CD.Object];

Create a standard cell object by performing the above operations

END.