DIRECTORY Core, CoreClasses, CoreCreate, CoreFlat, CoreOps, NewBasicRosemary; NewBasicRosemaryTest: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreOps, NewBasicRosemary = BEGIN OPEN NewBasicRosemary; CreateInverter: PROC [] RETURNS [cellType: CoreCreate.CellType] = { In: CoreCreate.Wire _ CoreOps.CreateWire[name: "In"]; Out: CoreCreate.Wire _ CoreOps.CreateWire[name: "Out"]; Gnd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Gnd"]; Vdd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Vdd"]; ntrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Out, Gnd]], type: CoreClasses.CreateTransistor[nE] ]]; ptrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Out, Vdd, Vdd]], type: CoreClasses.CreateTransistor[pE] ]]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], instances: LIST [ntrans, ptrans], name: "Inverter" ]; }; Create2Inverter: PROC [] RETURNS [cellType: CoreCreate.CellType] = { In: CoreCreate.Wire _ CoreOps.CreateWire[name: "In"]; Out: CoreCreate.Wire _ CoreOps.CreateWire[name: "Out"]; Gnd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Gnd"]; Vdd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Vdd"]; Intern: CoreCreate.Wire _ CoreOps.CreateWire[name: "Intern"]; InInternOut: CoreCreate.Wire _ CoreCreate.WireList[LIST[In, Intern, Out], "InInternOut"]; inverter: CoreCreate.CellType _ CreateInverter[]; first: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [In, Intern, Gnd, Vdd]], type: inverter ]]; second: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [ actual: CoreOps.CreateWire[LIST [Intern, Out, Gnd, Vdd]], type: inverter ]]; cellType _ CoreClasses.CreateRecordCell[ public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, Intern, InInternOut]], instances: LIST [first, second], name: "Inverter2" ]; }; Test: PROC = { cellType: CoreCreate.CellType _ Create2Inverter[]; simulation: RoseSimulation _ NIL; internFlatWire: CoreFlat.FlatWireRec _ CoreFlat.ParseWirePath[cellType, "Intern"]; Intern, In, Out: RoseProbe _ NIL; [] _ SetNamedFixedWire[cellType, "Vdd", H]; [] _ SetNamedFixedWire[cellType, "Gnd", L]; simulation _ Instantiate[cellType]; Intern _ CreateProbe[simulation, internFlatWire]; [In, Out] _ BindProbes[simulation, cellType, "In", "Out"]; PL[In, H]; Settle[simulation]; IF GL[Out]#H THEN ERROR; IF GL[Intern]#L THEN ERROR; PL[In, L]; Settle[simulation]; IF GL[Out]#L THEN ERROR; IF GL[Intern]#H THEN ERROR; }; Test[]; END. ‚NewBasicRosemaryTest.mesa Copyright Σ 1988 by Xerox Corporation. All rights reserved. Barth, June 9, 1988 3:42:24 pm PDT ΚΘ˜codešœ™Kšœ<™