
    <<NewRosemaryTest.mesa>>
        <<Copyright © 1986 by Xerox Corporation.  All rights reserved.>>
        <<Barth, June 9, 1988 3:42:24 pm PDT>>
    <<>>
    DIRECTORY BitOps, Core, CoreClasses, CoreCreate, CoreFlat, CoreOps, Ports, Rosemary, RosemaryUser, RosemaryVector;

    NewRosemaryTest: CEDAR PROGRAM
        IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreOps, Ports, Rosemary, RosemaryUser, RosemaryVector
        = BEGIN

    CreateInverter: PROC [] RETURNS [cellType: CoreCreate.CellType] = {
    In: CoreCreate.Wire _ CoreOps.CreateWire[name: "In"];
    Out: CoreCreate.Wire _ CoreOps.CreateWire[name: "Out"];
    Gnd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Gnd"];
    Vdd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Vdd"];
    ntrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [
    actual: CoreOps.CreateWire[LIST [In, Out, Gnd]], 
    type: CoreClasses.CreateTransistor[nE]
    ]];
    ptrans: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [
    actual: CoreOps.CreateWire[LIST [In, Out, Vdd, Vdd]], 
    type: CoreClasses.CreateTransistor[pE]
    ]];
    cellType _ CoreClasses.CreateRecordCell[
    public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], 
    internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], 
    instances: LIST [ntrans, ptrans],
    name: "Inverter"
    ];
    };

    Create2Inverter: PROC [] RETURNS [cellType: CoreCreate.CellType] = {
    In: CoreCreate.Wire _ CoreOps.CreateWire[name: "In"];
    Out: CoreCreate.Wire _ CoreOps.CreateWire[name: "Out"];
    Gnd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Gnd"];
    Vdd: CoreCreate.Wire _ CoreOps.CreateWire[name: "Vdd"];
    Intern: CoreCreate.Wire _ CoreOps.CreateWire[name: "Intern"];
    InInternOut: CoreCreate.Wire _ CoreCreate.WireList[LIST[In, Intern, Out], "InInternOut"];
    inverter: CoreCreate.CellType _ CreateInverter[];
    first: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [
    actual: CoreOps.CreateWire[LIST [In, Intern, Gnd, Vdd]], 
    type: inverter
    ]];
    second: CoreClasses.CellInstance _ NEW [CoreClasses.CellInstanceRec _ [
    actual: CoreOps.CreateWire[LIST [Intern, Out, Gnd, Vdd]], 
    type: inverter
    ]];
    cellType _ CoreClasses.CreateRecordCell[
    public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]], 
    internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, Intern, InInternOut]], 
    instances: LIST [first, second],
    name: "Inverter2"
    ];
    };
    <<>>
    in, out, gnd, vdd: NAT _ LAST[NAT];

    Test: PROC = {

    CheckIntern: PROC [checkIntern: BOOL, bit: Ports.Level] = {
        IF checkIntern THEN {
            value: Ports.LevelSequence _ Rosemary.WireValue[sim, flatWire];
            IF value.size#1 THEN ERROR;
            IF value[0]#bit THEN ERROR;
            };
    };

    SimpleTest: PROC [checkIntern: BOOL _ FALSE] = {
        p[in].l _ H;
        Rosemary.Settle[sim];
        IF p[out].l#H THEN ERROR;
        CheckIntern[checkIntern, L];
        p[in].l _ L;
        Rosemary.Settle[sim];
        IF p[out].l#L THEN ERROR;
        CheckIntern[checkIntern, H];
    };

    cellType: CoreCreate.CellType _ Create2Inverter[];
        p: Ports.Port _ NIL;
        sim: Rosemary.Simulation _ NIL;
        cutSet: CoreFlat.CutSet _ CoreFlat.CreateCutSet[cellTypes: LIST["Inverter2"]];
        flatWire: CoreFlat.FlatWire _ NEW[CoreFlat.FlatWireRec _ CoreFlat.ParseWirePath[cellType, "Intern"]];
        InitPorts[cellType.public];
        [] _ Rosemary.SetFixedWire[cellType.public[vdd], H];
        [] _ Rosemary.SetFixedWire[cellType.public[gnd], L];
        [] _ Ports.InitPort[wire: cellType.public[in], levelType: l, initDrive: none];
        [] _ Ports.InitTesterDrive[wire: cellType.public[in], initDrive: force];
        [] _ Ports.InitPort[wire: cellType.public[out], levelType: l, initDrive: drive];
        [] _ Ports.InitTesterDrive[wire: cellType.public[out], initDrive: none];
        p _ Ports.CreatePort[cellType, TRUE];
        sim _ Rosemary.Instantiate[cellType, p, cutSet];
        SimpleTest[];
        sim _ Rosemary.Instantiate[cellType, p];
        SimpleTest[TRUE];
        [] _ RosemaryUser.TestProcedureViewer[cellType, LIST["Inverter2Test"], "Inverter2Test", 
        RosemaryUser.DisplayPortLeafWires[cellType]];
    };

    InitPorts: PROC [public: CoreCreate.Wire] = {
        in _ Ports.PortIndex[public, "In"];
        out _ Ports.PortIndex[public, "Out"];
        gnd _ Ports.PortIndex[public, "Gnd"];
        vdd _ Ports.PortIndex[public, "Vdd"];
        };

    Inverter2Simple: Rosemary.EvalProc = {
        p[out].l _ p[in].l;
        };

    Inverter2Test: RosemaryUser.TestProc = {
        testPort: Ports.Port _ Ports.CreatePort[cellType];
        target: RosemaryVector.Target _ NIL;
    vector: RosemaryVector.VectorFile _ RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: testPort, read: FALSE];
    flatCell: CoreFlat.FlatCellType _ NEW[CoreFlat.FlatCellTypeRec _ CoreFlat.ParseCellTypePath[cellType, "/0"]];
    flatCellPublic: Core.Wire _ CoreFlat.ResolveFlatCellType[simulation.cellType, flatCell^].cellType.public;
        target _ RosemaryVector.CreateTarget[simulation, flatCell, testPort];
        InitPorts[cellType.public];
        THROUGH [0..100) DO
            p[out].l _ p[in].l _ H;
            Eval[];
        RosemaryVector.SampleTarget[target, testPort];
        RosemaryVector.WriteVector[vector];
            p[out].l _ p[in].l _ L;
            Eval[];
        RosemaryVector.SampleTarget[target, testPort];
        RosemaryVector.WriteVector[vector];
            ENDLOOP;
    RosemaryVector.CloseVectorFile[vector];
        vector _ RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: testPort, read: TRUE];
        THROUGH [0..100) DO
            p[out].l _ p[in].l _ H;
            Eval[];
        RosemaryVector.ReadVector[vector];
        Ports.CheckPortValueEqual[flatCellPublic, p, testPort];
            p[out].l _ p[in].l _ L;
            Eval[];
        RosemaryVector.ReadVector[vector];
        Ports.CheckPortValueEqual[flatCellPublic, p, testPort];
            ENDLOOP;
        };

TestVector: PROC = {
wire: CoreCreate.Wire _ CoreCreate.WireList[LIST["level", CoreCreate.Seq["levelSequence", 2], "bool", 
CoreCreate.Seq["boolSequence", 2], CoreCreate.Seq["cardinal", 2], CoreCreate.Seq["longCardinal", 2], CoreCreate.Seq["quadWord", 
2]]];
cell: Core.CellType _ CoreClasses.CreateUnspecified[wire];
writePort, readPort: Ports.Port;
vector: RosemaryVector.VectorFile;
[] _ Ports.InitPort[wire[0], l];
[] _ Ports.InitPort[wire[1], ls];
[] _ Ports.InitPort[wire[2], b];
[] _ Ports.InitPort[wire[3], bs];
[] _ Ports.InitPort[wire[4], c];
[] _ Ports.InitPort[wire[5], lc];
[] _ Ports.InitPort[wire[6], q];
writePort _ Ports.CreatePort[cell];
writePort[0].d _ force;
writePort[0].l _ H;
writePort[1].d _ force;
FOR i: NAT IN [0..2) DO
writePort[1].ls[i] _ H;
ENDLOOP;
writePort[2].d _ force;
writePort[2].b _ TRUE;
writePort[3].d _ force;
FOR i: NAT IN [0..2) DO
writePort[3].bs[i] _ TRUE;
ENDLOOP;
writePort[4].d _ force;
writePort[4].c _ 1023;
writePort[5].d _ force;
writePort[5].lc _ 85;
writePort[6].d _ force;
writePort[6].q _ BitOps.BitQWordOnes;
    vector _ RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: writePort, read: FALSE];
RosemaryVector.WriteVector[vector];
RosemaryVector.WriteVector[vector];
RosemaryVector.CloseVectorFile[vector];
readPort _ Ports.CreatePort[cell];
vector _ RosemaryVector.OpenVectorFile[fileName: "VectorTest.tioga", port: readPort, read: TRUE];
RosemaryVector.ReadVector[vector];
Ports.CheckPortValue[wire, writePort, readPort];
RosemaryVector.ReadVector[vector];
Ports.CheckPortValue[wire, writePort, readPort];
};

    [] _ Rosemary.Register[roseClassName: "Inverter2", evalSimple: Inverter2Simple];
    RosemaryUser.RegisterTestProc["Inverter2Test", Inverter2Test];

    END.