<> <> <> <<>> DIRECTORY BitOps, Core, CoreClasses, CoreFlat, RefTab, Rope; NewRosemary: CEDAR DEFINITIONS = BEGIN <> <> ROPE: TYPE = Rope.ROPE; Stop: SIGNAL [msg: ROPE _ NIL, data: REF ANY _ NIL, reason: ATOM _ $Client]; <> <> BindCellType: PROC [cellType: Core.CellType, roseClassName: ROPE] RETURNS [sameCellType: Core.CellType]; BindCellClass: PROC [cellClass: Core.CellClass, roseClassName: ROPE] RETURNS [sameCellClass: Core.CellClass]; Register: PROC [roseClassName: ROPE, init: InitProc _ NIL, evalSimple: EvalProc _ NIL, scheduleIfClockEval: BOOL _ FALSE] RETURNS [sameRoseClassName: ROPE]; InitProc: TYPE = PROC [simulation: Simulation, cellType: Core.CellType, flatCellType: CoreFlat.FlatCellType, oldStateAny: REF ANY _ NIL] RETURNS [stateAny: REF ANY _ NIL, stateValue: LevelSequence _ NIL]; <> <<>> EvalProc: TYPE = PROC [stateAny: REF ANY, clockEval: BOOL] RETURNS [stateValue: LevelSequence _ NIL]; <> <> <> <<>> SetFixedWire: PROC [wire: Core.Wire, level: Level _ L] RETURNS [sameWire: Core.Wire]; <> SetWireSize: PROC [wire: Core.Wire, size: WireSize _ charge] RETURNS [sameWire: Core.Wire]; WireSize: TYPE = Drive[chargeWeak..chargeStrong]; SetWireLevel: PROC [wire: Core.Wire, level: Level _ X] RETURNS [sameWire: Core.Wire]; SetWireMemory: PROC [wire: Core.Wire, memory: BOOL _ FALSE] RETURNS [sameWire: Core.Wire]; <> <<>> SetTransistorCellTypeSize: PROC [transistor: Core.CellType, size: TransistorSize] RETURNS [sameTransistor: Core.CellType]; <> SetTransistorInstanceSize: PROC [transistor: CoreClasses.CellInstance, size: TransistorSize] RETURNS [sameTransistor: CoreClasses.CellInstance]; TransistorSize: TYPE = Drive[driveWeak..driveStrong]; Instantiate: PROC [cellType: Core.CellType, cutSet: CoreFlat.CutSet _ NIL] RETURNS [simulation: RoseSimulation]; <> <> Initialize: PROC [simulation: RoseSimulation, updateCellProc: UpdateCellProc _ NIL]; <> <<>> Settle: PROC [simulation: RoseSimulation, memory: BOOL _ TRUE, clockEval: BOOL _ FALSE, updateWireProc: UpdateWireProc _ NIL, updateCellProc: UpdateCellProc _ NIL]; UpdateWireProc: TYPE = PROC [roseWire: RoseWire]; UpdateCellProc: TYPE = PROC [roseInstance: RoseCellInstance, stateValue: LevelSequence]; <> <<>> <> NotInstantiated: SIGNAL; <> <<>> GetWireValue: PROC [simulation: RoseSimulation, flatWire: CoreFlat.FlatWire] RETURNS [value: LevelSequence]; <> GetStateRef: PROC [simulation: RoseSimulation, flatCell: CoreFlat.FlatCellType] RETURNS [stateAny: REF ANY]; <> <<>> <> <> CreatePorts: PROC [simulation: RoseSimulation, flatWire: CoreFlat.FlatWire] RETURNS [ports: RosePorts]; <> <<>> BindPort: PROC [simulation: RoseSimulation, cell: Core.CellType, flatCell: CoreFlat.FlatCellType, name: Rope.ROPE] RETURNS [p: RosePorts]; <> BindPorts: PROC [simulation: RoseSimulation, cell: Core.CellType, flatCell: CoreFlat.FlatCellType, n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11: Rope.ROPE _ NIL] RETURNS [p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11: RosePorts _ NIL]; <> <<>> <> GetDrive, GD: PROC [p: RosePorts] RETURNS [v: Drive]; <> PutDrive, PD: PROC [p: RosePorts, v: Drive]; GetDriveSequence, GDS: PROC [p: RosePorts, i: NAT] RETURNS [v: Drive]; PutDriveSequence, PDS: PROC [p: RosePorts, i: NAT, v: Drive]; <> GetLevel, GL: PROC [p: RosePorts] RETURNS [v: Level]; PutLevel, PL: PROC [p: RosePorts, v: Level, d: Drive _ drive]; GetLevelSequence, GLS: PROC [p: RosePorts, i: NAT] RETURNS [v: Level]; PutLevelSequence, PLS: PROC [p: RosePorts, i: NAT, v: Level, d: Drive _ drive]; GetBool, GB: PROC [p: RosePorts] RETURNS [v: BOOL]; PutBool, PB: PROC [p: RosePorts, v: BOOL, d: Drive _ drive]; GetBoolSequence, GBS: PROC [p: RosePorts, i: NAT] RETURNS [v: BOOL]; PutBoolSequence, PBS: PROC [p: RosePorts, i: NAT, v: BOOL, d: Drive _ drive]; GetWord, GW: PROC [p: RosePorts] RETURNS [v: BitOps.BitWord]; PutWord, PW: PROC [p: RosePorts, v: BitOps.BitWord, d: Drive _ drive]; GetDWord, GDW: PROC [p: RosePorts] RETURNS [v: BitOps.BitDWord]; PutDWord, PDW: PROC [p: RosePorts, v: BitOps.BitDWord, d: Drive _ drive]; GetQWord, GQW: PROC [p: RosePorts] RETURNS [v: BitOps.BitQWord]; PutQWord, PQW: PROC [p: RosePorts, v: BitOps.BitQWord, d: Drive _ drive]; <> Not: PROC [src, dst: RosePorts]; Copy: PROC [src, dst: RosePorts]; Set: PROC [p: RosePorts, v: Level]; AnyX: PROC [p: RosePorts] RETURNS [BOOL]; ToRope: PROC [p: RosePorts, size: NAT _ 0, base: NAT _ 16] RETURNS [r: Rope.ROPE]; < all of them>> Size: PROC [p: RosePorts] RETURNS [size: NAT]; <> Level: TYPE = {L, H, X}; LevelSequence: TYPE = REF LevelSequenceRec; LevelSequenceRec: TYPE = RECORD [ s: PACKED SEQUENCE size: NAT OF Level]; Drive: TYPE = { inspect, -- allows test port to receive value expect, -- allows test port to specify expected value none, --in a test port it means neither driven nor checked; in an eval port it means no strength at all chargeWeak, chargeMediumWeak, charge, chargeMediumStrong, chargeStrong, force, -- weakest drive level, allows test procs to check if device has tristated driveWeak, driveMediumWeak, drive, driveMediumStrong, driveStrong, infinite -- drive for nodes which have infinite current sources }; DriveSequence: TYPE = REF DriveSequenceRec; DriveSequenceRec: TYPE = RECORD [ s: PACKED SEQUENCE size: NAT OF Drive]; RoseSimulation: TYPE = REF RoseSimulationRec; RoseSimulationRec: PUBLIC TYPE = RECORD [ cellType: Core.CellType _ NIL, coreToRoseWires: RefTab.Ref _ NIL, coreToRoseInstances: RefTab.Ref _ NIL, instanceNeedEval: RoseCellInstance _ NIL, instanceNeedEvalWhenNotClockEval: RoseCellInstance _ NIL, perturbed: RoseWire _ NIL, vicinityByStrength: ARRAY Drive OF VicinityRec, time: INT _ 0]; VicinityRec: TYPE = RECORD[ wires: RoseWires, firstFree: CARDINAL _ 0]; RoseCellType: TYPE = REF RoseCellTypeRec; RoseCellTypeRec: TYPE = RECORD [ init: InitProc _ NIL, evalSimple: EvalProc _ NIL, scheduleIfClockEval: BOOL _ FALSE]; RoseCellInstances: TYPE = LIST OF RoseCellInstance; RoseCellInstance: TYPE = REF RoseCellInstanceRec; RoseCellInstanceRec: TYPE = RECORD [ nextNeedEval: RoseCellInstance _ NIL, nextNeedEvalWhenNotClockEval: RoseCellInstance _ NIL, roseCellType: RoseCellType _ NIL, state: REF ANY _ NIL, log: RoseLog _ NIL, flatCellType: CoreFlat.FlatCellTypeRec]; RoseWireList: TYPE = LIST OF RoseWire; RoseWires: TYPE = REF RoseWireSeq; RoseWireSeq: TYPE = RECORD [s: SEQUENCE size: CARDINAL OF RoseWire]; RoseWire: TYPE = REF RoseWireRec; RoseWireRec: TYPE = RECORD [ ports: RosePorts _ NIL, nextPerturbedWire: RoseWire _ NIL, previousPerturbedWire: RoseWire _ NIL, nextRecomputed: RoseWire _ NIL, nextVicinityWire: RoseWire _ NIL, channels: RoseTransistors _ NIL, notOffChannels: RoseTransistors _ NIL, validNotOffChannels: CARDINAL _ 0, gates: RoseTransistors _ NIL, switchDrive: Drive _ none, upDrive: Drive _ none, downDrive: Drive _ none, wireDrive: Drive _ charge, wireValue: Level _ L, mark: BOOL _ FALSE, memory: BOOL _ FALSE, log: RoseLog _ NIL, flatWire: CoreFlat.FlatWireRec]; RoseTransistors: TYPE = REF RoseTransistorSeq; RoseTransistorSeq: TYPE = RECORD [s: SEQUENCE size: CARDINAL OF RoseTransistor]; RoseTransistor: TYPE = REF RoseTransistorRec; RoseTransistorRec: TYPE = RECORD [ gate: RoseWire _ NIL, ch1: RoseWire _ NIL, ch2: RoseWire _ NIL, conductivity: Drive _ drive, transistorType: CoreClasses.TransistorType _ nE, flatCellType: CoreFlat.FlatCellTypeRec]; RosePorts: TYPE = REF RosePortSeq; RosePortSeq: TYPE = RECORD [s: SEQUENCE size: CARDINAL OF RosePort]; RosePort: TYPE = REF RosePortRec; RosePortRec: TYPE = RECORD [ instance: RoseCellInstance _ NIL, level: Level _ X, drive: Drive _ none, wire: RoseWire _ NIL]; <> <<>> RoseLog: TYPE = REF RoseLogRec; RoseLogRec: TYPE = RECORD [ lastFilePos: INT _ -1, -- the file position of the last sample written list: RoseSampleList _ NIL, -- if non-nil, the samples for this object are currently kept in memory previous: RoseSample _ NIL, -- the previous sample currentTime: INT _ -1, -- time of current sample current: RoseSample _ NIL]; -- the sample currently taken, not guaranteed if time=lastUpdateTime ???? what is time and lastUpdateTime RB <> <<- current.next = NIL>> <<- current.time = value of time at last call to Update>> <<- current will never be modified once time of Update call > current.time>> <<- previous is the sample that was valid just before current. It is necessary to allow collapsing current with a previous value. previous has not yet been written to disk!>> <<- if previous#NIL, then previous.next=current>> <<- if list#NIL, then samples are kept in memory. Then, either list.head=previous=NIL, or previous may be reached by following next links from list.head (possibly 0 times!).>> <<>> RoseSampleList: TYPE = REF RoseSampleListRec; RoseSampleListRec: TYPE ~ RECORD [ head: RoseSample, -- the head of the list. The tail is always LogData.current beforeHeadPos: INT, -- the file position of the predecessor of head, <0 => no predecessor inTable: BOOL _ FALSE]; -- used internally to RBT management, don't modify <> RoseSample: TYPE = REF RoseSampleRec; RoseSampleRec: TYPE = RECORD [ next: RoseSample _ NIL, time: INT _ LAST[INT], -- time at which this event occured value: PACKED SEQUENCE size: CARDINAL OF Level]; <> <<>> END.