NewBasicRosemaryTest.mesa
Copyright Ó 1988 by Xerox Corporation. All rights reserved.
Barth, June 9, 1988 3:42:24 pm PDT
DIRECTORY Core, CoreClasses, CoreCreate, CoreFlat, CoreOps, NewBasicRosemary;
NewBasicRosemaryTest:
CEDAR
PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreOps, NewBasicRosemary
= BEGIN OPEN NewBasicRosemary;
CreateInverter:
PROC []
RETURNS [cellType: CoreCreate.CellType] = {
In: CoreCreate.Wire ← CoreOps.CreateWire[name: "In"];
Out: CoreCreate.Wire ← CoreOps.CreateWire[name: "Out"];
Gnd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Gnd"];
Vdd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Vdd"];
ntrans: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Out, Gnd]],
type: CoreClasses.CreateTransistor[nE]
]];
ptrans: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Out, Vdd, Vdd]],
type: CoreClasses.CreateTransistor[pE]
]];
cellType ← CoreClasses.CreateRecordCell[
public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
instances: LIST [ntrans, ptrans],
name: "Inverter"
];
};
Create2Inverter:
PROC []
RETURNS [cellType: CoreCreate.CellType] = {
In: CoreCreate.Wire ← CoreOps.CreateWire[name: "In"];
Out: CoreCreate.Wire ← CoreOps.CreateWire[name: "Out"];
Gnd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Gnd"];
Vdd: CoreCreate.Wire ← CoreOps.CreateWire[name: "Vdd"];
Intern: CoreCreate.Wire ← CoreOps.CreateWire[name: "Intern"];
InInternOut: CoreCreate.Wire ← CoreCreate.WireList[LIST[In, Intern, Out], "InInternOut"];
inverter: CoreCreate.CellType ← CreateInverter[];
first: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [In, Intern, Gnd, Vdd]],
type: inverter
]];
second: CoreClasses.CellInstance ←
NEW [CoreClasses.CellInstanceRec ← [
actual: CoreOps.CreateWire[LIST [Intern, Out, Gnd, Vdd]],
type: inverter
]];
cellType ← CoreClasses.CreateRecordCell[
public: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd]],
internal: CoreOps.CreateWire[LIST [In, Out, Gnd, Vdd, Intern, InInternOut]],
instances: LIST [first, second],
name: "Inverter2"
];
};
Test:
PROC = {
cellType: CoreCreate.CellType ← Create2Inverter[];
simulation: RoseSimulation ← NIL;
internFlatWire: CoreFlat.FlatWireRec ← CoreFlat.ParseWirePath[cellType, "Intern"];
Intern, In, Out: RoseProbe ← NIL;
[] ← SetNamedFixedWire[cellType, "Vdd", H];
[] ← SetNamedFixedWire[cellType, "Gnd", L];
simulation ← Instantiate[cellType];
Intern ← CreateProbe[simulation, internFlatWire];
[In, Out] ← BindProbes[simulation, cellType, "In", "Out"];
PL[In, H];
Settle[simulation];
IF GL[Out]#H THEN ERROR;
IF GL[Intern]#L THEN ERROR;
PL[In, L];
Settle[simulation];
IF GL[Out]#L THEN ERROR;
IF GL[Intern]#H THEN ERROR;
};
Test[];
END.