<> <> <> <<>> DIRECTORY Core, CoreClasses, CoreFlat, RefTab, Rope; NewBasicRosemary: CEDAR DEFINITIONS = BEGIN <> SetFixedWire: PROC [wire: Core.Wire, level: Level _ L] RETURNS [sameWire: Core.Wire]; <> SetNamedFixedWire: PROC [cellType: Core.CellType, name: Rope.ROPE, level: Level _ L] RETURNS [sameWire: Core.Wire]; <> Instantiate: PROC [cellType: Core.CellType] RETURNS [simulation: RoseSimulation]; Initialize: PROC [simulation: RoseSimulation]; <<>> Settle: PROC [simulation: RoseSimulation]; <<>> <> <> CreateProbe: PROC [simulation: RoseSimulation, flatWire: CoreFlat.FlatWireRec] RETURNS [probe: RoseProbe]; <> <<>> BindProbe: PROC [simulation: RoseSimulation, cellType: Core.CellType, name: Rope.ROPE, flatCell: CoreFlat.FlatCellTypeRec _ CoreFlat.rootCellType] RETURNS [probe: RoseProbe]; <> BindProbes: PROC [simulation: RoseSimulation, cellType: Core.CellType, n0, n1, n2, n3, n4: Rope.ROPE _ NIL, flatCell: CoreFlat.FlatCellTypeRec _ CoreFlat.rootCellType] RETURNS [p0, p1, p2, p3, p4: RoseProbe _ NIL]; <> <<>> <> <> <<>> GetLevel, GL: PROC [p: RoseProbe] RETURNS [v: Level]; GetBool, GB: PROC [p: RoseProbe] RETURNS [v: BOOL]; GetInt, GI: PROC [p: RoseProbe] RETURNS [v: INT32]; GetCardinal, GC: PROC [p: RoseProbe] RETURNS [v: CARD32]; <> <> <<>> PutLevel, PL: PROC [p: RoseProbe, v: Level, d: Drive _ drive]; PutBool, PB: PROC [p: RoseProbe, v: BOOL, d: Drive _ drive]; PutInt, PI: PROC [p: RoseProbe, v: INT32, d: Drive _ drive]; PutCardinal, PC: PROC [p: RoseProbe, v: CARD32, d: Drive _ drive]; <> <> <<>> GetProbeDrive, GPD: PROC [p: RoseProbe, index: NAT _ 0] RETURNS [d: Drive]; GetProbeLevel, GPL: PROC [p: RoseProbe] RETURNS [v: Level]; GetProbeBool, GPB: PROC [p: RoseProbe] RETURNS [v: BOOL]; GetProbeInt, GPI: PROC [p: RoseProbe] RETURNS [v: INT32]; GetProbeCardinal, GPC: PROC [p: RoseProbe] RETURNS [v: CARD32]; <> FindLevel: PROC [levelID: Rope.ROPE] RETURNS [level: Level]; FindDrive: PROC [driveID: Rope.ROPE] RETURNS [drive: Drive]; <> Level: TYPE = {L, H, X}; levelNames: ARRAY Level OF Rope.ROPE; Drive: TYPE = { inspect, -- allows test port to receive value expect, -- allows test port to specify expected value none, --in a test port it means neither driven nor checked; in an eval port it means no strength at all chargeWeak, chargeMediumWeak, charge, chargeMediumStrong, chargeStrong, force, -- weakest drive level, allows test procs to check if device has tristated driveWeak, driveMediumWeak, drive, driveMediumStrong, driveStrong, infinite -- drive for nodes which have infinite current sources }; driveNames: ARRAY Drive OF Rope.ROPE; WireSize: TYPE = Drive[chargeWeak..chargeStrong]; RoseSimulation: TYPE = REF RoseSimulationRec; RoseSimulationRec: PUBLIC TYPE = RECORD [ cellType: Core.CellType _ NIL, coreToRoseWires: RefTab.Ref _ NIL, perturbed: RoseWire _ NIL, vicinityByStrength: ARRAY Drive OF VicinityRec, settle: INT _ 0, step: INT _ 0]; VicinityRec: TYPE = RECORD[ wires: RoseWires, firstFree: CARDINAL _ 0]; RoseWires: TYPE = REF RoseWireSeq; RoseWireSeq: TYPE = RECORD [s: SEQUENCE size: CARDINAL OF RoseWire]; RoseWire: TYPE = REF RoseWireRec; RoseWireRec: TYPE = RECORD [ nextPerturbedWire: RoseWire _ NIL, previousPerturbedWire: RoseWire _ NIL, nextRecomputed: RoseWire _ NIL, nextVicinityWire: RoseWire _ NIL, probes: RoseProbePrimitives _ NIL, channels: RoseTransistors _ NIL, notOffChannels: RoseTransistors _ NIL, gates: RoseTransistors _ NIL, switchDrive: Drive _ none, upDrive: Drive _ none, downDrive: Drive _ none, wireSize: Drive _ charge, wireLevel: Level _ X, mark: BOOL _ FALSE, flatWire: CoreFlat.FlatWireRec]; RoseTransistors: TYPE = LIST OF RoseTransistor; RoseTransistor: TYPE = REF RoseTransistorRec; RoseTransistorRec: TYPE = RECORD [ gate: RoseWire _ NIL, ch1: RoseWire _ NIL, ch2: RoseWire _ NIL, conductivity: Drive _ drive, transistorType: CoreClasses.TransistorType _ nE, flatCellType: CoreFlat.FlatCellTypeRec]; RoseProbe: TYPE = REF RoseProbeRec; RoseProbeRec: TYPE = RECORD [ simulation: RoseSimulation _ NIL, s: SEQUENCE size: CARDINAL OF RoseProbePrimitive]; RoseProbePrimitives: TYPE = LIST OF RoseProbePrimitive; RoseProbePrimitive: TYPE = REF RoseProbePrimitiveRec; RoseProbePrimitiveRec: TYPE = RECORD [ level: Level _ X, drive: Drive _ none, wire: RoseWire _ NIL]; END.