NewBasicRosemary.mesa
Copyright Ó 1988 by Xerox Corporation. All rights reserved.
Barth, June 10, 1988 10:32:03 am PDT
DIRECTORY Core, CoreClasses, CoreFlat, RefTab, Rope;
NewBasicRosemary: CEDAR DEFINITIONS = BEGIN
Instantiation and Relaxation
SetFixedWire: PROC [wire: Core.Wire, level: Level ← L] RETURNS [sameWire: Core.Wire];
Sets the value of the wire and indicates that the value of the wire may not be changed by Rosemary. This is only intended to be used for atomic public wires of the root cell type such as Vdd and Gnd. These wires partition the network into disjoint blocks connected through transistor gates. It is not a general purpose mechanism for jamming a value onto a wire.
SetNamedFixedWire: PROC [cellType: Core.CellType, name: Rope.ROPE, level: Level ← L] RETURNS [sameWire: Core.Wire];
Same as SetFixedWire but uses name as the full name in the public of cellType.
Instantiate: PROC [cellType: Core.CellType] RETURNS [simulation: RoseSimulation];
Initialize: PROC [simulation: RoseSimulation];
Settle: PROC [simulation: RoseSimulation];
Probe
Creation
CreateProbe: PROC [simulation: RoseSimulation, flatWire: CoreFlat.FlatWireRec] RETURNS [probe: RoseProbe];
Creates an ordered set of Rosemary wires which correspond to the atomic Core wires of flatWire.
BindProbe: PROC [simulation: RoseSimulation, cellType: Core.CellType, name: Rope.ROPE, flatCell: CoreFlat.FlatCellTypeRec ← CoreFlat.rootCellType] RETURNS [probe: RoseProbe];
Same as CreateProbe but uses name as a full wire name in the public of cell to create the flatWire passed to CreateProbe.
BindProbes: PROC [simulation: RoseSimulation, cellType: Core.CellType, n0, n1, n2, n3, n4: Rope.ROPE ← NIL, flatCell: CoreFlat.FlatCellTypeRec ← CoreFlat.rootCellType] RETURNS [p0, p1, p2, p3, p4: RoseProbe ← NIL];
Same as BindProbe but for a pile of them.
Sample
All of these routines return the current value of the wire, not the value last put into the probe.
GetLevel, GL: PROC [p: RoseProbe] RETURNS [v: Level];
GetBool, GB: PROC [p: RoseProbe] RETURNS [v: BOOL];
GetInt, GI: PROC [p: RoseProbe] RETURNS [v: INT32];
GetCardinal, GC: PROC [p: RoseProbe] RETURNS [v: CARD32];
Drive
These routines change the value and drive of a probe.
PutLevel, PL: PROC [p: RoseProbe, v: Level, d: Drive ← drive];
PutBool, PB: PROC [p: RoseProbe, v: BOOL, d: Drive ← drive];
PutInt, PI: PROC [p: RoseProbe, v: INT32, d: Drive ← drive];
PutCardinal, PC: PROC [p: RoseProbe, v: CARD32, d: Drive ← drive];
Access
These routines return the the value last put into the probe, not current value of the wire. They are provided purely to complete the procedural abstraction.
GetProbeDrive, GPD: PROC [p: RoseProbe, index: NAT ← 0] RETURNS [d: Drive];
GetProbeLevel, GPL: PROC [p: RoseProbe] RETURNS [v: Level];
GetProbeBool, GPB: PROC [p: RoseProbe] RETURNS [v: BOOL];
GetProbeInt, GPI: PROC [p: RoseProbe] RETURNS [v: INT32];
GetProbeCardinal, GPC: PROC [p: RoseProbe] RETURNS [v: CARD32];
Utilities
FindLevel: PROC [levelID: Rope.ROPE] RETURNS [level: Level];
FindDrive: PROC [driveID: Rope.ROPE] RETURNS [drive: Drive];
Data Structures
Level: TYPE = {L, H, X};
levelNames: ARRAY Level OF Rope.ROPE;
Drive: TYPE = {
inspect, -- allows test port to receive value
expect, -- allows test port to specify expected value
none, --in a test port it means neither driven nor checked; in an eval port it means no strength at all
chargeWeak, chargeMediumWeak,
charge,
chargeMediumStrong, chargeStrong,
force, -- weakest drive level, allows test procs to check if device has tristated
driveWeak, driveMediumWeak,
drive,
driveMediumStrong, driveStrong,
infinite -- drive for nodes which have infinite current sources
};
driveNames: ARRAY Drive OF Rope.ROPE;
WireSize: TYPE = Drive[chargeWeak..chargeStrong];
RoseSimulation: TYPE = REF RoseSimulationRec;
RoseSimulationRec: PUBLIC TYPE = RECORD [
cellType: Core.CellType ← NIL,
coreToRoseWires: RefTab.Ref ← NIL,
perturbed: RoseWire ← NIL,
vicinityByStrength: ARRAY Drive OF VicinityRec,
settle: INT ← 0,
step: INT ← 0];
VicinityRec: TYPE = RECORD[
wires: RoseWires,
firstFree: CARDINAL ← 0];
RoseWires: TYPE = REF RoseWireSeq;
RoseWireSeq: TYPE = RECORD [s: SEQUENCE size: CARDINAL OF RoseWire];
RoseWire: TYPE = REF RoseWireRec;
RoseWireRec: TYPE = RECORD [
nextPerturbedWire: RoseWire ← NIL,
previousPerturbedWire: RoseWire ← NIL,
nextRecomputed: RoseWire ← NIL,
nextVicinityWire: RoseWire ← NIL,
probes: RoseProbePrimitives ← NIL,
channels: RoseTransistors ← NIL,
notOffChannels: RoseTransistors ← NIL,
gates: RoseTransistors ← NIL,
switchDrive: Drive ← none,
upDrive: Drive ← none,
downDrive: Drive ← none,
wireSize: Drive ← charge,
wireLevel: Level ← X,
mark: BOOL ← FALSE,
flatWire: CoreFlat.FlatWireRec];
RoseTransistors: TYPE = LIST OF RoseTransistor;
RoseTransistor: TYPE = REF RoseTransistorRec;
RoseTransistorRec: TYPE = RECORD [
gate: RoseWire ← NIL,
ch1: RoseWire ← NIL,
ch2: RoseWire ← NIL,
conductivity: Drive ← drive,
transistorType: CoreClasses.TransistorType ← nE,
flatCellType: CoreFlat.FlatCellTypeRec];
RoseProbe: TYPE = REF RoseProbeRec;
RoseProbeRec: TYPE = RECORD [
simulation: RoseSimulation ← NIL,
s: SEQUENCE size: CARDINAL OF RoseProbePrimitive];
RoseProbePrimitives: TYPE = LIST OF RoseProbePrimitive;
RoseProbePrimitive: TYPE = REF RoseProbePrimitiveRec;
RoseProbePrimitiveRec: TYPE = RECORD [
level: Level ← X,
drive: Drive ← none,
wire: RoseWire ← NIL];
END.