A summary block diagram is given in Figure 1. (not yet done ...)

The MTS board has 4 connectors T1, T2, T3, T4 plus the PC/AT extension bus connector. T1 through T4 are 40 pin flat cable connectors. All odd-numbered pins are grounded to improve noise immunity and signal cross-talk. They should also be grounded on the test fixture side.

The other pins are connected as follows:

T4.26 through T4.40 must not be connected to anything on the test fixture since the +5V power supplies may be slightly different. T4.24 may be grounded externally. T4.20 and T4.22 are connected only on a master board (they are N.C. on slave boards through jumper J3).

Normally, T1, T2 and T3 are connected to the text fixture to provide 60 effective channels. The 4 remaining channels are not normally accessible. The T4 connectors of all the boards are connected pin for pin. Moreover, the test fixture may use the nPass and nFail lines to light 2 LEDs (connect positive side to one of +5V lines, the negative side to nPass or nFail) and may provide a push-button grounding StartTest to indicate to the test software that a chip has been inserted and may be tested.

Jumpers J1/J2 determine the board address (bits A4 to A19). J1 contains the least-significant address bits, J2 the most significant address bits. If a jumper is present, the address bit is matched when it is 0, if the jumper is absent, the address bit matches when it is a 1 (jumpers are set vertically).

To set J1/J2 correctly, the best technique is to hold the board upside-down (PC connector on top). The J2 is on the left, J1 on the right, and the 16-bit segment address of the board can be set in binary notation: leftmost J1 is most significant bit, rightmost bit of J2 is least significant bit).

The standard segment address for the first board is $CD01, which translates into:

The MTS software expects board 1 to be a master board and all other boards to be slave boards (c.f. corresponding section for jumper positions). The slot positions used by boards are of no concern to the software, but they should be placed with boards in increasing numbers when looking from left to right when one is placed in front of the PC/AT or expansion chassis.

Jumpers P2/P3 define whether the board is memory-mapped or IO-mapped. The test software assumes memory mapping, so these jumpers should never be changed from their default setting which is memory mapped.

The top row of P2/P3 is named P2, the bottom is P3. The jumpers have only 2 valid positions (PC conector on top):

When multiple boards are used, one of them is a master board and all others are slave. The master board is the only one on which reading registers 8 through 15 has any significance. The software expects board # 1 ($CD01) to be the master board, and all slave boards to have increasing consecutive addresses ($CD02 and so on).

Whether a board is master or slave is defined by jumpers P4/P5, J3 and J4. The top row of P4/P5 is P4, the bottom row is P5. The jumpers have the following valid positions (PC conector on top):

Ports T1, T2, T3 each carry 20 test channels on the even-numbered pins and Gnd on the odd-numbered pins. Refer to section 1 for exact pin-out information. A test fixture may use any of these connectors to provide test channels. The Gnd pins must be connected to Gnd on the fixture side also to ensure proper signal shielding.

Port T4 is a control port. It contain 4 additional channels that cannot be used by a test fixture. All the T4 ports of all the boards must be connected together to propagate clocking information properly. Although all connections are not necessary, it is simpler to just connect all T4 connectors pin-for-pin. This chain should also connect a fixture add-on that provides:

When testing a board (test settings of the jumpers), this add-on test-fixture should also connect together pins 10, 12 and 14 of T4 to ensure proper clocking.

An MTS board controls 64 channels on the tester numbered from 0 to 64. This corresponds to 3 accessible 64-bit registers:

Reg0 contains the least significant byte of Reg (DOut, DIn or Drv) whereas Reg7 contains the most significant byte.

Pseudo-registers have side effects when read (all are byte registers):

The MTS board is accessible as 16 8-bit registers located in memory or IO space according to an on-board jumper. All current software for the MTS board assumes memory mapping. The registers behave differently on read and write.