DIRECTORY Core, CoreClasses, CoreFlat, RefTab, IO, MintPrivate, PlotGraph, Rope, Schedule; Mint: CEDAR DEFINITIONS ~ BEGIN ps: TYPE = REAL; -- picosecond (1e-12 s) mVolt: TYPE = REAL; -- millivolt (1e-3 V) pF: TYPE = REAL; -- picofarad (1e-12 F) Circuit: TYPE = REF CircuitRec; -- global handle CircuitRec: TYPE = RECORD [ rootCell: Core.CellType, nodeTable: RefTab.Ref, agenda: Schedule.Agenda _ NIL, library: Library _ NIL, fetTypeList: LIST OF FetType, info: MintPrivate.Info, private: MintPrivate.MintPrivateData ]; NodeList: TYPE = LIST OF Node; NodeSeq: TYPE = REF NodeSeqRec; NodeSeqRec: TYPE = RECORD [elements: SEQUENCE size: NAT OF Node]; Node: TYPE = REF NodeRec; -- others call them wires NodeRec: TYPE = RECORD [ flatWire: CoreFlat.FlatWire, history: Schedule.History, --Last notables events around cap: REAL, --Intrinsic capacitance. fetSeq: FetSeq, --fets connnecting to this node. setList: SetList, --sets connnecting their inputs to this node. prevNodeU, prevNodeD: Node, --pointers to previous nodes in longest path search. index: CARDINAL, --index of this node in various sequences and matrices input, --node forced to a fixed value by outside world. watched, --means the value of the node is used by the outside world fixedV, --this node is a power node tiedToDir, --is the ch2 of a directional fet ignoreMe, done, exactValue: BOOLEAN _ FALSE ]; FetList: TYPE = LIST OF Fet; FetSeq: TYPE = REF FetSeqRec; FetSeqRec: TYPE = RECORD [nUsed: NAT _ 0, elements: SEQUENCE size: NAT OF Fet]; Fet: TYPE = REF FetRec; FetRec: TYPE = RECORD [ gate, ch1, ch2: Node, --Nodes connecting to transistor. type: FetType, --Type of transistor switch, --TRUE means that the fet is turn on directional, --means the fet lets flow information fron ch1 to ch2 only done: BOOLEAN _ FALSE --multi purpose flag ]; FetType: TYPE = REF FetTypeRec; FetTypeRec: TYPE = RECORD [ l: NAT, -- transistor length w: NAT, -- transistor width type: CoreClasses.TransistorType, rOnInv: REAL -- Inverse of equivalent resistance when the fet is on ]; SetList: TYPE = LIST OF Set; SetSeq: TYPE = REF SetSeqRec; SetSeqRec: TYPE = RECORD [elements: SEQUENCE size: NAT OF Set]; Set: TYPE = REF SetRec; --two fets are in the same set iff there is a path between them SetRec: TYPE = RECORD [ --following sources and drains lFets: FetList _ NIL, lNodes: NodeList _ NIL, --nodes connecting the fets of the set inList: NodeList _ NIL, --other nodes connected to the gates of the fets (set inputs) fixedV: NodeList _ NIL, --nodes fixed by the outside world (like Vdd and Gnd) type: SetType _ NIL, selfInputs: BOOLEAN _ FALSE, --some nodes of the set are connected to gates of its fets done: BOOLEAN _ FALSE --multi purpose flag ]; SetType: TYPE = REF SetTypeRec; -- some figures allowing easy recognition of simple structures SetTypeRec: TYPE = RECORD [ nFets: ARRAY CoreClasses.TransistorType OF CARDINAL _ ALL[0], nVddTran, nGndTran, nNodes, nInput: CARDINAL _ 0, solve: SolveProc _ NIL ]; SolveProc: TYPE = PROC[set: Set, t: ps, circuit: Circuit] RETURNS [nextTime: ps]; Library: TYPE = LIST OF LibraryElem _ NIL; -- the sets accessed by SetType. LibraryElem: TYPE = REF LibraryElemRec; LibraryElemRec: TYPE = RECORD [ type: SetType, nElem: CARDINAL _ 0, setList: SetList _ NIL ]; TypeTable: ARRAY CoreClasses.TransistorType OF TType; -- for physical constants TType: TYPE = REF TTypeRec; TTypeRec: TYPE = RECORD [ name: Rope.ROPE, cPerArea, cPerWidth: REAL, rOn: REAL ]; StdOut: IO.STREAM; discardMe: ATOM; -- $MintDiscardMe. CreateCircuit: PROC [rootCell: Core.CellType, layout: BOOLEAN _ TRUE, eachPublicWireCapa: pF _ 0.0] RETURNS [circuit: Circuit]; InputData: PROC [circuit: Circuit, fixedVList: NodeList, layout: BOOLEAN _ TRUE, eachWireCapa: pF _ 0.0]; NodeFromRope: PROC [id: Rope.ROPE, circuit: Circuit] RETURNS [node: Node]; RopeFromNode: PROC [node: Node, circuit: Circuit] RETURNS [id: Rope.ROPE]; SetNode: PROC [node: Node, val, input: BOOLEAN _ TRUE, t: ps _ 0.0]; GetNode: PROC [node: Node] RETURNS [val: BOOLEAN]; EditNodeHistory: PROC [node: Node, t: ps, v: mVolt]; EditNodeInputBool: PROC [node: Node, forcedInput: BOOLEAN]; SettledValuesOfNode: PROC [node: Node] RETURNS [t: ps, v: mVolt]; CircuitSimulate: PROC[circuit: Circuit, from: ps _ 0.0] RETURNS [t: ps]; InteractiveSimulate: PROC [circuit: Circuit, watchList: NodeList _ NIL, from: ps _ 0.0]; DrawNodeList: PROC [nodeList: NodeList, circuit: Circuit] RETURNS[plot: PlotGraph.Plot]; AddNodeToPlot: PROC [node: Node, plot: PlotGraph.Plot, r: Rope.ROPE _ NIL]; CheckLibrary: PROC [circuit: Circuit]; CheckRatios: PUBLIC PROC [circuit: Circuit]; OutputResults: PROC [circuit: Circuit]; ignoreMe: ATOM; -- $MintIgnoreMe. see also $MintDiscardMe upper. oneWay: ATOM; -- $MintOneWay. RecordPaths: PROC [circuit: Circuit, clkList: NodeList] RETURNS [worst: ps _ 0.0]; PathArray: TYPE = REF PathArrayRec; PathArrayRec: TYPE = RECORD [table: SEQUENCE size: NAT OF PathArrayEl]; PathArrayEl: TYPE = RECORD [t: ps, nOfPaths: NAT _ 1, node: Node]; FindSlowestPaths: PROC [circuit: Circuit, n: NAT _ 1, noExactValues: BOOLEAN _ FALSE] RETURNS [veryLastTime: ps, slowNodes: PathArray]; Show: PROC [name: Rope.ROPE, circuit: Circuit]; PrintFet: PROC [fet: Fet, circuit: Circuit]; PrintNode: PROC [node: Node, circuit: Circuit]; PrintFetList: PROC [fetList: FetList, circuit: Circuit]; PrintFetSeq: PROC [fetSeq: FetSeq, circuit: Circuit]; PrintNodeList: PROC [nodeList: NodeList, circuit: Circuit]; PrintPath: PROC [to: Node, circuit: Circuit]; PrintPathUp: PROC [to: Node, circuit: Circuit]; PrintPathDown: PROC [to: Node, circuit: Circuit]; PrintPathArray: PROC [pA: PathArray, circuit: Circuit]; KillFetList: PROC [fetList: FetList]; KillNodeList: PROC [nodeList: NodeList]; KillSetList: PROC [setList: SetList, killSets: BOOLEAN _ TRUE]; KillCircuit: PROC [circuit: Circuit]; END. Mint.mesa Copyright Σ 1986, 1987 by Xerox Corporation. All rights reserved. Christian Le Cocq January 26, 1988 6:30:35 pm PST UNITS set: Set, --the static set which contains this node(no longer unique) Input from Core This prop stops the input from core for that cell or instance if set to $TRUE. For Mint this cell is empty. create the empty data structure with only the top level public, so that one can specify the power nodes before actually constructing the "Circuit" with InputData. Builds the handle of Mint data from the Core structures. If NOT layout then eachWireCapa will be added to each wire above the level of the cells having a $Get or $GetAndFlatten Layout atom. The basic cells wires will have no parasitic capacitance added. Specification A Node name is the CoreFlat name of the highest internal CoreFlat wire of the equipotential. Finds the node with the specified (ROPE) name. gives the rope name of the node. Read and write the node structure as a logical wire (booleans are converted to Gnd & Vdd): edits the value of the node for t. gives the last value of the node Read and write the node structure as an electrical wire: The basic way to specify the stimuli. The events must be edited in time order, a modification of the middle of the history deletes the end of the history from this time. Specifies the fact that a node is or is not a voltage source. Vdd and Gnd are inputs. gives the last value of the node Simulation & Display Build the initial calendar of events and simulate until a steady state is reached. the same as CircuitSimulate except that it builds and refreshes a display. Builds the oscilloscope that display this list of Nodes. Appends a graph showing node to plot, using r as a name if specified. Electrical Checking Verify the static connectivity: isolated nodes, nodes that cannot be driven, node not reachable from Vdd or Gnd. Verify that each node can be turned on and off by each "contributing" node (i.e. checks the NMos ratios in particular) Print the statistics of the library on the number and types of sets created by PrepareSets. Timing Analysis This prop stops the analysis of a path for timing if set to $TRUE. Could be on a celltype, instance or wire. This prop transforms a fet into a directional device which let only flows information from ch1 to ch2. Used to unscrew multiplexers. writes into the circuit data structure the longest path to each node. gives the n slowest Path (after MaxFreqEvaluate has written the data structures). It gives only one PathArrayRec RECORD for each "kind" of path. It means that the following heuristics apply: the data of a path which has the same chain of timing than an other one is not given, and the nOfPaths field of the other one is increased; a path which appears inside a path already recorded is discarded. noExactValues means that the timing of known signals (i.e. clocks) is not listed. Utilities Prints as much relevant information as possible for a given equipotential Prints the type, size, switch and ports of the fet. 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