<> <> <> <<>> <<>> DIRECTORY Core, CoreClasses, CoreFlat, RefTab, IO, MintPrivate, PlotGraph, Rope, Schedule; Mint: CEDAR DEFINITIONS ~ BEGIN <> ps: TYPE = REAL; -- picosecond (1e-12 s) mVolt: TYPE = REAL; -- millivolt (1e-3 V) pF: TYPE = REAL; -- picofarad (1e-12 F) Circuit: TYPE = REF CircuitRec; -- global handle CircuitRec: TYPE = RECORD [ rootCell: Core.CellType, nodeTable: RefTab.Ref, agenda: Schedule.Agenda _ NIL, library: Library _ NIL, fetTypeList: LIST OF FetType, info: MintPrivate.Info, private: MintPrivate.MintPrivateData ]; NodeList: TYPE = LIST OF Node; NodeSeq: TYPE = REF NodeSeqRec; NodeSeqRec: TYPE = RECORD [elements: SEQUENCE size: NAT OF Node]; Node: TYPE = REF NodeRec; -- others call them wires NodeRec: TYPE = RECORD [ flatWire: CoreFlat.FlatWire, history: Schedule.History, --Last notables events around cap: REAL, --Intrinsic capacitance. fetSeq: FetSeq, --fets connnecting to this node. <> setList: SetList, --sets connnecting their inputs to this node. prevNodeU, prevNodeD: Node, --pointers to previous nodes in longest path search. index: CARDINAL, --index of this node in various sequences and matrices input, --node forced to a fixed value by outside world. watched, --means the value of the node is used by the outside world fixedV, --this node is a power node tiedToDir, --is the ch2 of a directional fet ignoreMe, done, exactValue: BOOLEAN _ FALSE ]; FetList: TYPE = LIST OF Fet; FetSeq: TYPE = REF FetSeqRec; FetSeqRec: TYPE = RECORD [nUsed: NAT _ 0, elements: SEQUENCE size: NAT OF Fet]; Fet: TYPE = REF FetRec; FetRec: TYPE = RECORD [ gate, ch1, ch2: Node, --Nodes connecting to transistor. type: FetType, --Type of transistor switch, --TRUE means that the fet is turn on directional, --means the fet lets flow information fron ch1 to ch2 only done: BOOLEAN _ FALSE --multi purpose flag ]; FetType: TYPE = REF FetTypeRec; FetTypeRec: TYPE = RECORD [ l: NAT, -- transistor length w: NAT, -- transistor width type: CoreClasses.TransistorType, rOnInv: REAL -- Inverse of equivalent resistance when the fet is on ]; SetList: TYPE = LIST OF Set; SetSeq: TYPE = REF SetSeqRec; SetSeqRec: TYPE = RECORD [elements: SEQUENCE size: NAT OF Set]; Set: TYPE = REF SetRec; --two fets are in the same set iff there is a path between them SetRec: TYPE = RECORD [ --following sources and drains lFets: FetList _ NIL, lNodes: NodeList _ NIL, --nodes connecting the fets of the set inList: NodeList _ NIL, --other nodes connected to the gates of the fets (set inputs) fixedV: NodeList _ NIL, --nodes fixed by the outside world (like Vdd and Gnd) type: SetType _ NIL, selfInputs: BOOLEAN _ FALSE, --some nodes of the set are connected to gates of its fets done: BOOLEAN _ FALSE --multi purpose flag ]; SetType: TYPE = REF SetTypeRec; -- some figures allowing easy recognition of simple structures SetTypeRec: TYPE = RECORD [ nFets: ARRAY CoreClasses.TransistorType OF CARDINAL _ ALL[0], nVddTran, nGndTran, nNodes, nInput: CARDINAL _ 0, solve: SolveProc _ NIL ]; SolveProc: TYPE = PROC[set: Set, t: ps, circuit: Circuit] RETURNS [nextTime: ps]; Library: TYPE = LIST OF LibraryElem _ NIL; -- the sets accessed by SetType. LibraryElem: TYPE = REF LibraryElemRec; LibraryElemRec: TYPE = RECORD [ type: SetType, nElem: CARDINAL _ 0, setList: SetList _ NIL ]; TypeTable: ARRAY CoreClasses.TransistorType OF TType; -- for physical constants TType: TYPE = REF TTypeRec; TTypeRec: TYPE = RECORD [ name: Rope.ROPE, cPerArea, cPerWidth: REAL, rOn: REAL ]; StdOut: IO.STREAM; <> discardMe: ATOM; -- $MintDiscardMe. <> CreateCircuit: PROC [rootCell: Core.CellType, layout: BOOLEAN _ TRUE, eachPublicWireCapa: pF _ 0.0] RETURNS [circuit: Circuit]; <> InputData: PROC [circuit: Circuit, fixedVList: NodeList, layout: BOOLEAN _ TRUE, eachWireCapa: pF _ 0.0]; <> <> <> NodeFromRope: PROC [id: Rope.ROPE, circuit: Circuit] RETURNS [node: Node]; <> RopeFromNode: PROC [node: Node, circuit: Circuit] RETURNS [id: Rope.ROPE]; <> <<>> <> SetNode: PROC [node: Node, val, input: BOOLEAN _ TRUE, t: ps _ 0.0]; <> GetNode: PROC [node: Node] RETURNS [val: BOOLEAN]; <> <> EditNodeHistory: PROC [node: Node, t: ps, v: mVolt]; <> EditNodeInputBool: PROC [node: Node, forcedInput: BOOLEAN]; <> SettledValuesOfNode: PROC [node: Node] RETURNS [t: ps, v: mVolt]; <> <> CircuitSimulate: PROC[circuit: Circuit, from: ps _ 0.0] RETURNS [t: ps]; <> InteractiveSimulate: PROC [circuit: Circuit, watchList: NodeList _ NIL, from: ps _ 0.0]; <> DrawNodeList: PROC [nodeList: NodeList, circuit: Circuit] RETURNS[plot: PlotGraph.Plot]; <> AddNodeToPlot: PROC [node: Node, plot: PlotGraph.Plot, r: Rope.ROPE _ NIL]; <> <> CheckLibrary: PROC [circuit: Circuit]; <> CheckRatios: PUBLIC PROC [circuit: Circuit]; <> OutputResults: PROC [circuit: Circuit]; <> <> ignoreMe: ATOM; -- $MintIgnoreMe. see also $MintDiscardMe upper. <> oneWay: ATOM; -- $MintOneWay. <> RecordPaths: PROC [circuit: Circuit, clkList: NodeList] RETURNS [worst: ps _ 0.0]; <> PathArray: TYPE = REF PathArrayRec; PathArrayRec: TYPE = RECORD [table: SEQUENCE size: NAT OF PathArrayEl]; PathArrayEl: TYPE = RECORD [t: ps, nOfPaths: NAT _ 1, node: Node]; FindSlowestPaths: PROC [circuit: Circuit, n: NAT _ 1, noExactValues: BOOLEAN _ FALSE] RETURNS [veryLastTime: ps, slowNodes: PathArray]; <> <<>> <> Show: PROC [name: Rope.ROPE, circuit: Circuit]; <> PrintFet: PROC [fet: Fet, circuit: Circuit]; <> PrintNode: PROC [node: Node, circuit: Circuit]; <> PrintFetList: PROC [fetList: FetList, circuit: Circuit]; PrintFetSeq: PROC [fetSeq: FetSeq, circuit: Circuit]; PrintNodeList: PROC [nodeList: NodeList, circuit: Circuit]; PrintPath: PROC [to: Node, circuit: Circuit]; PrintPathUp: PROC [to: Node, circuit: Circuit]; PrintPathDown: PROC [to: Node, circuit: Circuit]; PrintPathArray: PROC [pA: PathArray, circuit: Circuit]; <<4 procs to improve GC use:>> KillFetList: PROC [fetList: FetList]; KillNodeList: PROC [nodeList: NodeList]; KillSetList: PROC [setList: SetList, killSets: BOOLEAN _ TRUE]; <> KillCircuit: PROC [circuit: Circuit]; END.