DIRECTORY IO, AbSets, LichenDataStructure;

LichenDataOps: CEDAR DEFINITIONS
=

BEGIN OPEN Sets:AbSets, LichenDataStructure;

CreateDesign: PROC [names: Set--of ROPE--] RETURNS [Design];

CheckDesign: PROC [d: Design];

CellFlavor: TYPE ~ {leaf, unorganized, array};

CreateCellType: PROC [d: Design, flavor: CellFlavor, names: Set--of ROPE--] RETURNS [CellType];
FinishCreatingUnorganized: PROC [ct: CellType];
CreateArray: PROC [d: Design, eltType: CellType, size, basePeriod: Int2, fXfm: Fn--phase _ Transform--, offsets: OffsetSeq, names: Set--of ROPE--] RETURNS [CellType];
CreateArrayPart: PROC [act, ect: CellType, size, basePeriod: Int2, fXfm: Fn, offsets: OffsetSeq] RETURNS [Array];
SetArrayPart: PROC [act, ect: CellType, a: Array];
TrimStatrep: PROC [act: CellType, a: Array, edges: Set--of StatEdge-- _ nilSet];
FinishedMakingArrayConnections: PROC [act: CellType];
ForgetUnorganized: PROC [ct: CellType];
ForgetArray: PROC [CellType];

OffsetsFromList: PROC [OffsetPatList] RETURNS [OffsetSeq];
OffsetPatList: TYPE ~ LIST OF OffsetPat;
CTIncludesPoint: PROC [CellType, Int2];
DesignScaleIs: PROC [Design, REAL];

CreatePort: PROC [ct: CellType, fullNames: Set--of SteppyName--, deduced, addum, nameDum, fixExpConns, fixInstConns, fixWExpConns, fixWInstConns: BOOL, children: Seq--of Port-- _ nilBiRel] RETURNS [Port];
CreateWire: PROC [ct: CellType, fullNames: Set--of SteppyName--, deduced, fixExpConns, fixInstConns: BOOL, children: Seq--of Wire-- _ nilBiRel] RETURNS [Wire];
Instantiate: PROC [ict, cct: CellType, addum: BOOL, xfm: Transform, offset: Int2, names: Set--of SteppyName--] RETURNS [CellInstance];

KnowPartName: PROC [ct: CellType, class: PartClass, part: Part, fullName: SteppyName, onlyIfGood: BOOL];
KnowPartNames: PROC [ct: CellType, class: PartClass, part: Part, fullNames: Set--of SteppyName--, onlyIfGood: BOOL];
ForgetPartName: PROC [ct: CellType, class: PartClass, part: Part, fullName: SteppyName];
ForgetPartNames: PROC [ct: CellType, class: PartClass, part: Part, fullNames: Set];
ReplaceDescendantsName: PROC [ct: CellType, subroot: PW, old, new: SteppyName];
ReplaceDescendantsNames: PROC [ct: CellType, subroot: PW, oldNew: BiRel--old SteppyName X new--];

KnowVertexName: PROC [ct: CellType, v: Vertex, fullName: SteppyName, onlyIfGood: BOOL]
~ INLINE {KnowPartName[ct, v.class, v, fullName, onlyIfGood]};
KnowVertexNames: PROC [ct: CellType, v: Vertex, fullNames: Set--of SteppyName--, onlyIfGood: BOOL]
~ INLINE {KnowPartNames[ct, v.class, v, fullNames, onlyIfGood]};
ForgetVertexName: PROC [ct: CellType, v: Vertex, fullName: SteppyName]
~ INLINE {ForgetPartName[ct, v.class, v, fullName]};

KnowPortName: PROC [ct: CellType, p: Port, fullName: SteppyName, onlyIfGood: BOOL]
~ INLINE {KnowPartName[ct, p, p, fullName, onlyIfGood]};
KnowPortNames: PROC [ct: CellType, p: Port, fullNames: Set--of SteppyName--, onlyIfGood: BOOL]
~ INLINE {KnowPartNames[ct, p, p, fullNames, onlyIfGood]};
ForgetPortName: PROC [ct: CellType, p: Port, fullName: SteppyName]
~ INLINE {ForgetPartName[ct, p, p, fullName]};

PortForWire: PROC [ct: CellType, internal: Wire, mayAdd: BOOL] RETURNS [port: Port];
FullySfwdlyExportWires: PROC [ct: CellType, wires: Set] RETURNS [Set--of Port--];
ExtractNamed: PROC [ct: CellType, names: Set] RETURNS [newPorts: Set];
GetArrayPortForPort: PROC [act: CellType, ai: Int2, ep: Port, mayAdd, addum, nameDum: BOOL] RETURNS [arrayPort: Port];
ImportAtomicWireOnce: PROC [d: Design, ct: CellType, from: Wire] RETURNS [port: Port, internal: Wire];
Connect: PROC [d: Design, wire: Wire, port: Port, site: Cell];
ConnectPWs: PROC [d: Design, pws: Fn, site: Cell];
ConnectPCs: PROC [d: Design, wire: Wire, pcs: BiRel];
ClosePortConnectivity: PROC [d: Design, parent: Port, kidPorts: Seq--of Port--, conns: Fn--Port _ Wire--, site: Cell];
ClosePortsConnectivity: PROC [d: Design, parents: Set--of Port--, conns: Fn--Port _ Wire--, site: Cell];
MakeArrayNewConnection: PROC [d: Design, a: Array, rangeA: Range2, delta: Int2, epA, epB: Port];
MakeArrayConnectionAtPhase: PROC [d: Design, a: Array, rangeA: Range2, fA, delta: Int2, epA, epB: Port];
MakeArrayExport: PROC [d: Design, a: Array, ap, ep: Port, ai: Int2];
NoteNewEltPort: PROC [act: CellType, ep: Port];
NoteNewArrayPort: PROC [act: CellType, ap: Port];
NoteExEltPorts: PROC [ect: CellType, eps: Set--of port--, mayHaveConsequences: BOOL, log: IO.STREAM _ NIL];
NoteEltPortMerge: PROC [ect: CellType, kept: Port, lost: Set--of port--];
MayDeletePorts: PROC [ct: CellType, ports: Set--of port--, timid, isWholeTrees: BOOL] RETURNS [whyNot: ROPE];

TryToMergeDumbWires: PROC [d: Design, act: CellType, wires: Set] RETURNS [balks: Set--of DumbWire--];

MergeNets: PROC [d: Design, w1, w2: Wire, callerWillTakeCareOfPorts: BOOL] RETURNS [merged, deleted: Wire];

MergeWireSet: PROC [d: Design, wires: Set, callerWillTakeCareOfPorts: BOOL] RETURNS [kept: Wire, lost: Set];

MergePorts: PROC [ct: CellType, ports: Set] RETURNS [kept: Port, lost: Set];

UndistinguishCellTypes: PROC [d: Design, lost, kept: CellType, assoc: OneToOne];

DeleteWires: PROC [ct: CellType, wires: Set, visitConns, lowerPortsToo: BOOL, log: IO.STREAM _ NIL, clip: Set--of CellType-- _ nilSet];

DeletePorts: PROC [ct: CellType, ports: Set, visitInsts, deleteWires, lowerWiresToo: BOOL, log: IO.STREAM _ NIL, clip: Set--of CellType-- _ nilSet];

DeleteInsts: PROC [d: Design, cis: Set, visitWires, killCTs: BOOL, log: IO.STREAM _ NIL];

DeleteCellType: PROC [ct: CellType, recurse: BOOL, log: IO.STREAM _ NIL];

DeleteCellTypes: PROC [cts: Set, recurse: BOOL, log: IO.STREAM _ NIL];

Differentiate: PROC [d: Design, cis: Set] RETURNS [new: CellType];

FixInterleavingsOfArray: PROC [act: CellType];

AddDeducedStructureToDesign: PUBLIC PROC [design: Design, pacify: IO.STREAM _ NIL];
DeduceStructureForWires: PROC [ct: CellType, pacify: IO.STREAM _ NIL] RETURNS [new: Set--of Wire--];
DeduceStructureForPorts: PROC [ct: CellType, pacify: IO.STREAM _ NIL] RETURNS [new: Set--of Port--];

PrefixifyDesign: PROC [Design];
DropPhysical: PROC [d: Design];
CleanDesign: PROC [d: Design, pacify: IO.STREAM _ NIL] RETURNS [losses: ARRAY EClass OF Set--of set of name--];

CreateBareWire: PROC [Design] RETURNS [Wire];
CreateBareInstance: PROC [d: Design, offset: Int2] RETURNS [CellInstance];
CreateBareDumbWire: PROC [act: CellType] RETURNS [DumbWire];
CreateDumbWireKids: PROC [a: Array, len: LNAT] RETURNS [Seq--of DumbWire--];

ExpandType: PROC [d: Design, ct: CellType] RETURNS [newCis: Set];
ExpandInstance: PROC [d: Design, ci: CellInstance] RETURNS [ciWas, wireWas: OneToOne];
UnorganizeArray: PROC [CellType];
DeduceArrayness: PROC [d: Design, cts: Set--of CellType--, pacify: IO.STREAM] RETURNS [oks: Set--of CellType--, errs: Fn--CellType _ err msg--];
FlattenArrays: PROC [d: Design, cts: Set--of CellType--, fix: BOOL, pacify: IO.STREAM] RETURNS [oks: Set--of CellType--, errs: Fn--CellType _ err msg--];
MinimizeArraysPeriod: PROC [d: Design, cts: Set--of CellType--, pacify: IO.STREAM] RETURNS [report: Fn--CellType _ period--];
LowerArrayStructure: PROC [outer: CellType];
SimilarizeArrays: PROC [d: Design, acts: Set--of CellType--] RETURNS [uncrossed: Set--of CellType--];

ReadRenames: PROC [d: Design, fileName: ROPE] RETURNS [renames: Fn--CellType _ Fn(old steppy _ new)--, renamesCount: INT];
InheritNames: PUBLIC PROC [design: Design, cleanup, collapse: BOOL, renames: Fn--CellType _ Fn(old steppy _ new)--];
CleanupDesignNames: PROC [d: Design];

ShortenArrayType: PROC [act: CellType, end: ArrayEnd, sDim: Dim3 _ Z, by: NAT _ 1, hackTypeNames: BOOL _ TRUE];
ShortenArrayInstance: PROC [d: Design, ci: CellInstance, end: ArrayEnd, sDim: Dim3 _ Z, by: NAT _ 1];

UndistinguishPorts: PROC [d: Design, pacify: IO.STREAM _ NIL] RETURNS [report: BiRel--cell type name X set of port name--];

ExtractPads: PROC [d: Design, log: IO.STREAM _ NIL] RETURNS [exCells: BiRel, newPorts: Set];

END.
�����LichenDataOps.Mesa
Last tweaked by Mike Spreitzer on May 11, 1989 6:30:22 pm PDT
Dummy wires are added iff addum; fixWExpConns and fixWInstConns tell whether to fix up connections to the dummies.

May only be invoked on top atomic wires.
May only be invoked on top wires.
If not callerWillTakeCareOfPorts, may only be invoked on private wires.
Like MergeNets, but operates on a set of wires.
All must export the same wire.  Works only for top ports.  Caller responsible for ensuring that implementation of ports survives.
assoc identifies ports.
Caller responsible for making sure impl of wires survives this operation.  If lowerPortsToo, logs & deletes ports to which this wire is connected, passing clip to DeletePorts.
Caller responsible for making sure impl of ports survives this operation.  If visitInsts, deletes connections at instances of ct, and fixes arrays of ct.  If a log is given, messages are printed to it for consequent deletions.  If lowerWiresToo, deletes the wires exported by these ports, unless ct is in clip.
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