<> <> DIRECTORY LichenDataStructure, Rope; Lichen: CEDAR DEFINITIONS = {OPEN LichenDataStructure; LORA: TYPE ~ LichenDataStructure.LORA; ROPE: TYPE ~ Rope.ROPE; Design: TYPE ~ LichenDataStructure.Design; Wire: TYPE ~ LichenDataStructure.Wire; RefSet: TYPE ~ REF LichenDataStructure.Set; KeyProc: TYPE ~ PROC [ <> RipoutTransistors: PROC [inA: REF ANY], RipoutInsts: PROC [parentA, cisA: REF ANY], MergeWireKludge: PROC [wiresA: REF ANY], <> ExternallyMerged: PROC [portsA: REF ANY], UndistinguishPorts: PROC, ImportAtomicWireOnceToRoot: PROC [name: ROPE] RETURNS [Wire], ImportAtomicWireOnce: PROC [ctA, fromA: REF ANY] RETURNS [Wire], ExportWires: PROC [ctA, wiresA: REF ANY], DeduceWireStructure: PROC, CleanupDesign: PROC, Group: PROC [iName, tName: ROPE, parentA, sibsA: REF ANY], ExpandInstance: PROC [instA: REF ANY], ExpandType: PROC [tName: ROPE], FlattenArrays: PROC, RaiseGCs: PROC [childA, gcsA: REF ANY] RETURNS [RefSet--of raised instances--], LowerKidsOnce: PROC [parentA, kidsA, sibA: REF ANY] RETURNS [loweredKids: RefSet--of CellInstance--], ShortenArrayInstance: PROC [inst: REF ANY, end: ArrayEnd, sDim: Dim3 _ Z, by: NAT _ 1], LowerArrayStructure: PROC [outerA: REF ANY], SimilarizeArrays: PROC, <> PrefixifyDesign: PROC, InheritNames: PROC [renamesFileName: ROPE], CleanupNames: PROC, DropPhysical: PROC, <> DeduceArrayness: PROC [ctsA: REF ANY], MinimizeArrayPeriods: PROC, <> Subcells: PROC [parentName: ROPE, instanceTypes, instanceNames: REF ANY] RETURNS [--constant--RefSet], <> At: PROC [INT], ReadExt: PROC [rootCellFileName, clippingFileName: ROPE, readPorts: BOOL, labelCellTypes: REF ANY], ExtractPads: PROC, ReadPorts: PROC [ROPE], ReadFunsim: PROC [rootName: ROPE] ]; Do: PROC [prefix, suffix: ROPE, Key: KeyProc, from, to: INT, startD: Design _ NIL] RETURNS [Design]; }.