DIRECTORY AbSets, BiRels, IntStuff, LichenDataOps, LichenDataStructure, LichenNavigation, LichenTransforms, LichenTransformsPrivate, RefTab; LichenChildishTransforms: CEDAR PROGRAM IMPORTS AbSets, BiRels, IntStuff, LichenDataOps, LichenDataStructure, LichenNavigation, RefTab EXPORTS LichenTransforms, LichenTransformsPrivate = BEGIN OPEN LichenDataStructure, LichenNavigation, LichenTransforms, LichenDataOps, LichenTransformsPrivate, Sets:AbSets; LowerChildren: PUBLIC PROC [design: Design, childType: CellType, sibber: ConstFunction--child _ Seq (role f sibling: Vertex)--] RETURNS [gcs: Seq--role f grandchild--] = BEGIN analysis: Analysis = NEW [AnalysisPrivate _ [ roles: LAST[NATURAL], wag: NEW [WireAnsweringPrivate _ [ anses: BiRels.CreateHashFn[] ]], doomedPorts: Sets.CreateHashSet[] ]]; IF childType.firstArray#NIL THEN ERROR nyet; {OPEN analysis; oldPort: Port ~ childType.port; newPort: Port ~ oldPort; first: BOOL _ TRUE; dif: BOOL _ FALSE; parentTypes: VarSet ~ Sets.CreateHashSet[]; childrenV: VarSet ~ Sets.CreateHashSet[]; {SeeInstance: PROC [child: CellInstance] = { sibs: Seq--role f sibling-- = BiRels.DeRef[sibber.ApplyA[child].MA]; IF IsMirror[child] THEN ERROR; --AM2 IF first THEN { wag.oldSubjConnectionss _ CreateRefSeq[roles _ sibs.Size.EN]; subjTypes _ sibs.Compose[right: instanceType, restricts: [TRUE, FALSE]].CreateVectorCopy[domainFixed: TRUE]; }; IF Survey[child.containingCT, child, sibs, analysis, first] THEN dif _ TRUE; first _ FALSE; }; EnumerateInstances[childType, SeeInstance, FALSE]; }; IF first OR dif THEN RETURN [BiRels.nilBiRel]; NoteChange[childType]; gcs _ CreateSeq[oneToOne: TRUE]; FOR role: NATURAL IN [0 .. roles) DO gcs.AppendA[Instantiate[ type: NARROW[subjTypes.ApplyI[role].MA], containingCT: childType]]; ENDLOOP; {MaybeDeleteOldChildPort: PROC [cPort: Port, w: Vertex, e: Edge] = { wire: Wire = NARROW[w]; IF doomedPorts.HasMemA[cPort] THEN RemoveEdges[e]; }; EnumerateTopEdges[childType.asUnorganized.mirror, MaybeDeleteOldChildPort]}; <<{PerTopWire: PROC [pair: BiRels.Pair] = { outerWire: Wire = NARROW[pair[left]]; wa: WireAns = NARROW[pair[right]]; NewPort: PROC RETURNS [insideNet: Wire] = { SELECT wa.doFrom FROM addPort => { wa.counterpart _ insideNet _ CreateWire[containingCT: childType, copy: outerWire]; wa.fromPort _ AddPort[[parent: newPort, wire: insideNet]]; AddEdge[[childType.asUnorganized.mirror, insideNet], wa.fromPort]; }; dePort => ERROR; leave, dontAdd => IF (insideNet _ wa.counterpart) = NIL THEN ERROR; ENDCASE => ERROR; RETURN}; MakeDummy: PROC RETURNS [insideNet: Wire] = { IF wa.counterpart # NIL THEN RETURN [wa.counterpart]; wa.counterpart _ insideNet _ CreateWire[containingCT: childType, copy: outerWire]; RETURN}; innerWire: Wire = IF wa.sawBord THEN wa.fromPort.wire ELSE IF wa.sawElse THEN NewPort[] ELSE MakeDummy[]; FOR subjPorts: RoledPortList _ wa.subjPorts, subjPorts.rest WHILE subjPorts # NIL DO gc: CellInstance ~ NARROW[gcs.ApplyI[subjPorts.first.role].MA]; AddEdges[[gc, innerWire], subjPorts.first.port]; design _ design; ENDLOOP; RETURN}; wag.anses.Enumerate[PerTopWire]; design _ design};>> FOR role: NATURAL IN [0 .. roles) DO rt: RefTable--subj port _ wire connected to that port of that subject at first site-- ~ NARROW[wag.oldSubjConnectionss[role]]; gc: CellInstance ~ NARROW[gcs.ApplyI[role].MA]; PerPort: PROC [gcPort: Port] RETURNS [subs, sibs: BOOL _ TRUE] ~ { urWire: Wire ~ NARROW[rt.Fetch[gcPort].val]; subs _ urWire=NIL; IF urWire#NIL THEN { wa: WireAns = GetRPAns[wag, role, gcPort, urWire, FALSE]; NewPort: PROC RETURNS [insideNet: Wire] = { SELECT wa.doFrom FROM addPort => { insideNet _ CreateWire[containingCT: childType, copy: urWire]; wa.fromPort _ AddPort[[parent: newPort, wire: insideNet]]; AddEdge[[childType.asUnorganized.mirror, insideNet], wa.fromPort]; }; dePort => ERROR; leave, dontAdd => ERROR; ENDCASE => ERROR; RETURN}; MakeDummy: PROC RETURNS [insideNet: Wire] = { insideNet _ CreateWire[containingCT: childType, copy: urWire]; RETURN}; IF wa.counterpart=NIL THEN wa.counterpart _ IF wa.sawBord THEN wa.fromPort.wire ELSE IF wa.sawElse THEN NewPort[] ELSE MakeDummy[]; {innerWire: Wire ~ wa.counterpart; AddEdges[[gc, innerWire], gcPort]; design _ design; }}; RETURN}; ScanPorts[gc.type, PerPort]; design _ design; ENDLOOP; CheckCellType[ct: childType, rep: ignore, norm: check, comparable: ignore, instances: FALSE]; {TweakInstance: PROC [child: CellInstance] = { sibs: Seq--role f sibling--; IF IsMirror[child] THEN ERROR; --AM2 [] _ childrenV.AddA[child]; sibs _ BiRels.DeRef[sibber.ApplyA[child].MA]; IF sibs.Size.EN # roles THEN ERROR --caller blew it--; FOR role: NATURAL IN [0 .. roles) DO sib: CellInstance = NARROW[sibs.ApplyI[role].MA]; PerEdge: PROC [gcPort: Port, net: Vertex, e: Edge] = { wa: WireAns = GetRPAns[wag, role, gcPort]; IF wa.sawElse AND NOT wa.sawBord THEN { IF wa.child # child THEN { AddEdges[[child, NARROW[net]], wa.fromPort]; wa.child _ child}; }; IF NOT (wa.sawElse OR wa.sawBords) THEN DeleteVertex[net] ELSE RemoveEdges[e]; }; IF sib.containingCT # child.containingCT THEN ERROR --caller blew it--; EnumerateTopEdges[sib, PerEdge]; DeleteVertex[sib]; ENDLOOP; NoteChange[child.containingCT]; [] _ parentTypes.AddA[child.containingCT]; }; EnumerateInstances[childType, TweakInstance, FALSE]}; CheckCellTypes[parentTypes.Freeze, ignore, check, ignore]; }END; RaiseGrandchildren: PUBLIC PROC [design: Design, gcs: Seq--role f instance in childType--] RETURNS [childType: CellType, sibber: ConstFunction--child _ Seq (role f sibling: Vertex)--, typer: ConstFunction--array*n of childType _ Seq (role f array*n of type of gcs[role])--] = BEGIN analysis: Analysis = NEW [AnalysisPrivate _ [ roles: gcs.Size.EN, subjTypes: gcs.Compose[instanceType].CreateVectorCopy[oneToOne: TRUE].Freeze, wag: NEW [WireAnsweringPrivate _ [ oldSubjConnectionss: CreateRefSeq[gcs.Size.EN], anses: BiRels.CreateHashFn[] ]], doomedPorts: Sets.CreateHashSet[] ]]; {OPEN analysis; addedPorts: VarSet = Sets.CreateHashSet[]; parentTypes: VarSet = Sets.CreateHashSet[]; sibberV: VarFunction ~ BiRels.CreateHashFn[]; childType _ NARROW[gcs.First.it[right].VA, CellInstance].containingCT; typer _ BiRels.CreateSingleton[[AV[childType], AV[subjTypes.Refify]], ALL[SetBasics.refs]]; IF childType.firstArray#NIL THEN ERROR nyet; FOR role: NAT IN [0 .. roles) DO gc: CellInstance ~ NARROW[gcs.ApplyI[role].MA]; IF gc.containingCT # childType THEN ERROR; ENDLOOP; {oldPort: Port ~ childType.port; newPort: Port ~ oldPort; IF Survey[childType, NIL, gcs, analysis, TRUE] THEN ERROR; {DeleteDoomed: PROC [elt: REF ANY] = {RemovePort[NARROW[elt]]}; doomedPorts.EnumA[DeleteDoomed]; }; {MaybeAddPort: PROC [left, right: REF ANY] ~ { wire: Wire ~ NARROW[left]; wa: WireAns ~ NARROW[right]; IF NOT wa.analyzed THEN ERROR; SELECT wa.doFrom FROM addPort => { wa.fromPort _ AddPort[[parent: newPort, wire: wire]]; [] _ addedPorts.AddA[wa.fromPort]; AddEdge[[childType.asUnorganized.mirror, wire], wa.fromPort]}; leave, dontAdd, dePort => NULL; ENDCASE => ERROR; }; wag.anses.EnumAA[MaybeAddPort]; }; < { wa.doFrom _ addedPort; wa.fromPort _ AddPort[[parent: newPort, wire: wire]]; [] _ addedPorts.AddElt[wa.fromPort]; AddEdge[[childType.asUnorganized.mirror, wire], wa.fromPort]}; addedPort => NULL; leave, dontAdd, dePort => NULL; ENDCASE => ERROR; }; }; EnumerateTopConnections[gc, PerEdge]; ENDLOOP;>> NoteChange[childType]; FOR role: NATURAL IN [0 .. roles) DO gc: CellInstance ~ NARROW[gcs.ApplyI[role].MA]; PerEdge: PROC [gcPort: Port, wire: Wire, e: Edge] = { wa: WireAns = GetRPAns[wag, role, gcPort, wire, FALSE]; IF NOT (wa.sawElse OR wa.sawBords) THEN DeleteVertex[wire] ELSE RemoveEdge[e]; }; EnumerateTopEdges[gc, PerEdge]; DeleteVertex[gc]; ENDLOOP; CheckCellType[ct: childType, rep: ignore, norm: check, comparable: ignore, instances: FALSE]; {FixInstance: PROC [child: CellInstance] = { sibs: Seq ~ CreateSeq[oneToOne: TRUE, dense: TRUE]; cons: RefTable--child port _ wire-- = CreateRefTable[]; IF IsMirror[child] THEN ERROR; --AM2 [] _ sibberV.AddAA[child, sibs.Refify]; FOR role: NATURAL IN [0 .. roles) DO gc: CellInstance = NARROW[gcs.ApplyI[role].MA]; sibs.AppendA[Instantiate[gc.type, child.containingCT]]; ENDLOOP; {PerConnection: PROC [cPort: Port, net: Vertex, ce: Edge] = { [] _ cons.Store[cPort, net]; IF doomedPorts.HasMemA[cPort] THEN RemoveEdges[ce]; }; EnumerateTopEdges[child, PerConnection]}; {LinkToNewPort: PROC [elt: REF ANY] = { cPort: Port = NARROW[elt]; outerNet: Wire = CreateWire[containingCT: child.containingCT, copy: cPort.wire]; IF cPort.wire=NIL THEN ERROR; AddEdges[[child, outerNet], cPort]; [] _ cons.Store[cPort, outerNet]; }; addedPorts.EnumA[LinkToNewPort]}; FOR role: NATURAL IN [0 .. roles) DO sib: CellInstance = NARROW[sibs.ApplyI[role].MA]; PerPort: PROC [gcPort: Port] = { wa: WireAns = GetRPAns[wag, role, gcPort]; MakeDummyNet: PROC [iNet: Wire] RETURNS [oNet: Wire] = { oNet _ wa.counterpart; IF oNet = NIL OR wa.child # child THEN { oNet _ CreateWire[containingCT: child.containingCT, copy: iNet]; wa.counterpart _ oNet; wa.child _ child; }; }; AddEdge[ [sib, IF wa.sawBord OR wa.sawElse THEN NARROW[cons.Fetch[wa.fromPort].val] ELSE MakeDummyNet[wa.proto]], gcPort]; }; EnumeratePorts[sib.type, PerPort]; ENDLOOP; NoteChange[child.containingCT]; [] _ parentTypes.AddA[child.containingCT]; }; EnumerateInstances[childType, FixInstance, FALSE]}; CheckCellTypes[parentTypes.Freeze, ignore, check, ignore]; sibber _ sibberV.Freeze[]; }}END; Survey: PUBLIC PROC [parent: CellType, child: Vertex, sibs: Seq--role f grandchild--, analysis: Analysis, first: BOOL] RETURNS [dif: BOOL _ FALSE] = { OPEN analysis; lwag: WireAnswering = NEW [WireAnsweringPrivate _ [CreateRefSeq[roles], BiRels.CreateHashFn[]]]; IF sibs.Size # subjTypes.Size THEN { Warning["Different number of siblings (%g, rather than %g) at %g", Int[sibs.Size.EI], Int[subjTypes.Size.EI], child]; dif _ TRUE} ELSE FOR role: NATURAL IN [0 .. roles) DO sib: CellInstance = NARROW[sibs.ApplyI[role].MA]; SeeConnection: PROC [gcPort: Port, wire: Wire] = { lwa: WireAns = GetRPAns[lwag, role, gcPort, wire, TRUE]; wa: WireAns = GetRPAns[wag, role, gcPort, wire, first]; SeeBackConnection: PROC [cPort: Port, v: Vertex] = { ci: CellInstance = NARROW[v]; bord: BOOL = IF child # NIL THEN ci=child ELSE IsMirror[ci]; IF bord THEN { lwa.sawBords _ lwa.sawBord; lwa.sawBord _ TRUE; lwa.fromPort _ cPort; } ELSE {sawSomeSelf: BOOL _ FALSE; FOR j: NATURAL IN [0 .. roles) DO IF ci = sibs.ApplyI[j].MA THEN sawSomeSelf _ lwa.sawSelves[j] _ TRUE; ENDLOOP; IF NOT sawSomeSelf THEN lwa.sawElse _ TRUE; }; RETURN}; IF NOT lwa.analyzed THEN { lwa.analyzed _ TRUE; lwa.sawSelves _ CreateBoolSeq[roles, FALSE]; EnumerateTransitiveConnections[wire, SeeBackConnection]; IF NOT lwa.sawSelves[role] THEN ERROR; IF first THEN { wa^ _ lwa^; IF wa.sawBord AND NOT (wa.sawElse OR wa.sawBords) THEN { losses _ NoteLoss[wa, losses]; IF NOT doomedPorts.AddA[wa.fromPort] THEN ERROR; }; IF wa.sawElse AND NOT wa.sawBord THEN fromGains _ NoteFromGain[wa, fromGains]; IF NOT (wa.sawElse OR wa.sawBord) THEN wa.doFrom _ dontAdd; IF wa.sawElse OR wa.sawBord THEN toGains _ NoteToGain[wa, toGains]; } ELSE { IF wa.sawBord # lwa.sawBord THEN GOTO Dif; IF wa.sawBords # lwa.sawBords THEN GOTO Dif; IF wa.sawElse # lwa.sawElse THEN GOTO Dif; FOR j: NATURAL IN [0 .. roles) DO IF wa.sawSelves[j] # lwa.sawSelves[j] THEN GOTO Dif; ENDLOOP; EXITS Dif => {Warning["%g is connected differently than at first site", wire]; dif _ TRUE}; }; }; IF first THEN { wa.subjPorts _ CONS[[role, gcPort], wa.subjPorts]; }; RETURN}; IF subjTypes.ApplyI[role].MA # sib.type THEN { Warning["%g is a %g, not a %g", sib, sib.type, subjTypes.ApplyI[role].MA]; dif _ TRUE} ELSE IF sib = child THEN { Warning["Child %g sibbed to itself", child]; dif _ TRUE} ELSE IF sib.containingCT # parent THEN ERROR ELSE { EnumerateTopConnections[sib, SeeConnection]; parent _ parent}; ENDLOOP; RETURN}; GetRPAns: PUBLIC PROC [wag: WireAnswering, role: NATURAL, subjPort: Port, wire: Wire _ NIL, mayChange: BOOL _ FALSE] RETURNS [wa: WireAns] = { kw: Wire; rt: RefTable _ NARROW[wag.oldSubjConnectionss[role]]; IF rt = NIL THEN { IF NOT mayChange THEN ERROR; wag.oldSubjConnectionss[role] _ rt _ CreateRefTable[]; }; IF wire = NIL THEN { wire _ NARROW[rt.Fetch[subjPort].val]; IF wire = NIL THEN ERROR; }; kw _ NARROW[rt.Fetch[subjPort].val]; IF kw = NIL THEN { IF NOT mayChange THEN ERROR; IF NOT rt.Insert[subjPort, kw _ wire] THEN ERROR}; IF wire # kw THEN ERROR; wa _ NARROW[wag.anses.ApplyA[wire].MDA]; IF wa = NIL THEN { IF NOT mayChange THEN ERROR; wa _ NEW [WireAnsPrivate _ [proto: wire]]; wag.anses.AddNewAA[wire, wa]; }; }; NoteLoss: PROC [wa: WireAns, oldLosses: CARDINAL] RETURNS [newLosses: CARDINAL] = { newLosses _ oldLosses; SELECT wa.doFrom FROM leave => {newLosses _ newLosses + 1; wa.doFrom _ dePort}; dePort => NULL; addPort, dontAdd => ERROR; ENDCASE => ERROR; }; NoteFromGain: PROC [wa: WireAns, oldGains: CARDINAL] RETURNS [newGains: CARDINAL] = { newGains _ oldGains; SELECT wa.doFrom FROM leave => {newGains _ newGains + 1; wa.doFrom _ addPort}; addPort => NULL; dePort, dontAdd => ERROR; ENDCASE => ERROR; }; NoteToGain: PROC [wa: WireAns, oldGains: CARDINAL] RETURNS [newGains: CARDINAL] = { newGains _ oldGains; SELECT wa.doTo FROM dontAdd => {newGains _ newGains + 1; wa.doTo _ addPort}; addPort => NULL; ENDCASE => ERROR; }; Int: PROC [i: INT] RETURNS [ra: REF ANY] = {ra _ NEW [INT _ i]}; END. fLichenChildishTransforms.Mesa Last tweaked by Mike Spreitzer on February 3, 1988 3:23:17 pm PST Κ‹˜™Icode™A—J˜KšΟk œƒ˜ŒK˜šΠbxœœ˜'KšœW˜^Kšœ*˜1Kšœ˜—K˜KšœœbΟnœ˜xK˜šŸ œœœ<ΟcΠcm  ‘ œœ  ‘  œ˜©Kš˜šœœ˜-Kšœœœ˜šœœ˜"Kšœ˜Kšœ˜—K˜!K˜—Kšœœœœ˜,Kšœœ ˜K˜K˜Kšœœœ˜Kšœœœ˜Kšœ+˜+Kšœ)˜)šœŸ œœ˜,Kšœ  ‘  œ%œ˜DKšœœœ ˜$šœœ˜Kšœ9œ˜=Kšœ:œœ!œ˜lKšœ˜—Kšœ:œœ˜LKšœœ˜K˜—Kšœ+œ˜2K˜Kšœœœœ˜.K˜Kšœœ˜ šœœœ˜$šœ˜Kšœœœ˜(Kšœ˜—Kšœ˜—šœŸœœ&˜DKšœ œ˜Kšœœ˜2K˜—KšœL˜LšœŸ œœ˜+Kšœœ ˜%Kšœœ˜"šŸœœœ˜+šœ ˜˜ KšœR˜RKšœ:˜:KšœB˜BK˜—Kšœ œ˜Kš œœ œœœ˜CKšœœ˜—Kšœ˜—šŸ œœœ˜-Kšœœœœ˜5KšœR˜RKšœ˜—Kš œœ œœœ œ œ ˜išœ9œ œ˜TKšœœ"œ˜?Kšœ0˜0K˜Kšœ˜—Kšœ˜—Kšœ ˜ K˜šœœœ˜$Kšœ   ‘ <œœ ˜~Kšœœœ˜/š Ÿœœœœœ˜BKšœœ˜,Kšœœ˜šœœœ˜Kšœ2œ˜9šŸœœœ˜+šœ ˜˜ Kšœ>˜>Kšœ:˜:KšœB˜BK˜—Kšœ œ˜Kšœœ˜Kšœœ˜—Kšœ˜—šŸ œœœ˜-Kšœ>˜>Kšœ˜—Kšœœœœ œœœ œ œ ˜ƒKšœ"˜"Kšœ"˜"K˜K˜—Kšœ˜—Kšœ˜K˜Kšœ˜—KšœVœ˜]šœŸ œœ˜.Kšœ  ‘  œ˜Kšœœœ ˜$Kšœ˜Kšœ)œ˜-Kš œ œ œœ œ˜6šœœœ˜$Kšœœœ˜1šŸœœ)˜6Kšœ*˜*šœ œœ œ˜'šœœ˜Kšœœ˜,Kšœ˜—K˜—Kš œœ œœœ˜NK˜—Kšœ'œœ œ˜GKšœ ˜ Kšœ˜Kšœ˜—K˜Kšœ*˜*K˜—Kšœ-œ˜5Kšœ:˜:Kšœœ˜—K˜šŸœœœ ‘ œœ, ‘  ‘ œ Πcu ‘  ‘ ’ œ˜“Kš˜šœœ˜-Kšœœ˜Kšœ@œ ˜Mšœœ˜"Kšœ+œ˜/Kšœ˜Kšœ˜—K˜!K˜—Kšœœ ˜K˜*Kšœ+˜+Kšœ-˜-Kšœ œœ˜FKšœ œ œœ˜[Kšœœœœ˜,šœœœ˜ Kšœœœ˜/Kšœœœ˜*Kšœ˜—K˜ K˜Kš œœœœœ˜:Kš œŸ œœœœœ˜?Kšœ ˜ K˜š œŸ œœœœ˜.Kšœ œ˜Kšœœ˜Kšœœ œœ˜šœ ˜šœ ˜ Kšœ5˜5Kšœ"˜"Kšœ>˜>—Kšœœ˜Kšœœ˜—K˜—Kšœ˜K˜šœœœ˜&Kšœœ ˜%šŸœœ˜,Kšœ0œ˜7Kšœœ œœ˜šœ œœ œ˜'šœ ˜šœ ˜ K˜Kšœ5˜5Kšœ$˜$Kšœ>˜>—Kšœ œ˜Kšœœ˜Kšœœ˜—K˜—K˜—Kšœ%˜%Kšœ˜ —K˜šœœœ˜$Kšœœœ˜/šŸœœ(˜5Kšœ0œ˜7Kš œœ œœœ˜NK˜—Kšœ˜K˜Kšœ˜—KšœVœ˜]šœŸ œœ˜,Kšœ œ œ˜3Kšœ  ‘ œ˜7Kšœœœ ˜$Kšœ'˜'šœœœ˜$Kšœœœ˜/Kšœ7˜7Kšœ˜—šœŸ œœ)˜=Kšœ˜Kšœœ˜3K˜—Kšœ)˜)š œŸ œœœœ˜'Kšœœ˜KšœP˜PKšœ œœœ˜Kšœ#˜#Kšœ!˜!K˜—K˜!šœœœ˜$Kšœœœ˜1šŸœœ˜ Kšœ*˜*šŸ œœœ˜8Kšœ˜šœœœœ˜(Kšœ@˜@Kšœ˜K˜K˜—K˜—šœ˜Kšœ˜šœ œ ˜Kšœœ˜(Kšœ˜—Kšœ˜—K˜—Kšœ"˜"Kšœ˜—Kšœ˜Kšœ*˜*K˜—Kšœ+œ˜3Kšœ:˜:Kšœ˜Kšœœ˜—K˜šŸœœœ, ‘  œœœœœ˜–Kšœ ˜KšœœG˜`šœœ˜$KšœQœœ ˜uKšœœ˜ —š œœœœ˜)Kšœœœ˜1šŸ œœ˜2Kšœ2œ˜8Kšœ7˜7šŸœœ˜4Kšœœ˜Kš œœœ œœ œ˜<šœœ˜Kšœ˜Kšœœ˜Kšœ˜Kšœ˜—šœœœ˜ šœœœ˜!Kšœœœ"œ˜EKšœ˜—Kšœœ œœ˜+Kšœ˜—Kšœ˜—šœœœ˜Kšœœ˜Kšœ%œ˜,Kšœ8˜8Kšœœœœ˜&šœœ˜K˜ š œ œœ œœ˜8K˜Kšœœœœ˜0K˜—Kšœ œœ œ)˜NKšœœ œ œ˜;Kšœ œ œ#˜CKšœ˜—šœ˜Kšœœœ˜*Kšœœœ˜,Kšœœœ˜*šœœœ˜!Kšœ$œœ˜4Kšœ˜—š˜KšœOœ˜U—Kšœ˜—Kšœ˜—šœœ˜Kšœœ˜2Kšœ˜—Kšœ˜—šœœ œ˜.KšœFœ˜JKšœœ˜ —šœœ œ˜Kšœ,˜,Kšœœ˜ —Kšœœœ˜,šœ˜Kšœ,˜,K˜—Kšœ˜—Kšœ˜—K˜šŸœœœœœ œœœ˜ŽK˜ Kšœœ ˜5šœœœ˜Kšœœ œœ˜Kšœ6˜6Kšœ˜—šœœœ˜Kšœœ˜&Kšœœœœ˜K˜—Kšœœ˜$šœœœ˜Kšœœ œœ˜Kšœœ œœ˜2—Kšœ œœ˜Kšœœœ˜(šœœœ˜Kšœœ œœ˜Kšœœ"˜*Kšœ˜K˜—K˜—K˜š Ÿœœœœ œ˜SK˜šœ ˜Kšœ9˜9Kšœ œ˜Kšœœ˜Kšœœ˜—K˜—K˜š Ÿ œœœœ œ˜UKšœ˜šœ ˜Kšœ8˜8Kšœ œ˜Kšœœ˜Kšœœ˜—K˜—K˜š Ÿ œœœœ œ˜SKšœ˜šœ ˜Kšœ8˜8Kšœ œ˜Kšœœ˜—K˜—K˜KšŸœœœœœœ œœ˜@K˜Kšœ˜—…—5~Go