LichenStatus.Tioga
Last tweaked by Mike Spreitzer on February 23, 1988 5:29:47 pm PST
Code:
- = not relevent
n = not thought about
N = not understood
u = allegedly somewhat understood
U = allegedly understood
b = implemented, but with suspected bug(s)
I = implemented
t = tested somewhat
T = tested a lot
WS = wire structure
A = arrays
M = meat (ports or wires are being created/deleted/merged)
IntroCellType U WS:-, A:-
ExtroCellType U WS:U, A:-
Differentiate U WS:-, A:U
Undifferentiate U WS:u, A:u
Just verify structural equivalence, and smash types. Can deduce port equivalences bottom-up!
LowerChildren t WS:u, A:U, M:N
RaiseGrandchildren t WS:u, A:U, M:N
MergeTypes n WS:u, A:u, M:N
SplitType t WS:u, A:I, M:N
GroupUnorganized I WS:u, A:u, M:N
Implemented in terms of LowerChildren + trivia that look insensitive to wire structure but sensitive to array issues.
ExpandUnorganized u WS:u, A:u, M:N
ExpandVertex I WS:b, A:u, M:N
ExpandChildren u WS:u, A:u, M:N
Flatten I WS:u, A:u, M:N
Implemented in terms of ExpandVertex + trivia that look insensitive to wire structure but sensitive to array issues.
RenameSteps t WS:t, A:t
PrefixifyDesign T WS:-, A:T
InheritNames T WS:-, A:T
AddDeducedStructureToDesign T WS:t, A:T
ReOrderDesign T WS:T, A:T