LichenDataOps:
CEDAR
DEFINITIONS
IMPORTS AbSets, LichenDataStructure
=
BEGIN OPEN Sets:AbSets, LichenDataStructure;
EnsureAllIn:
PROC [design: Design];
= ct deisgn : EnsurePrivate[ct]
EnsurePublic:
PROC [ct: CellType];
Make sure interface is fully defined.
EnsurePrivate:
PROC [ct: CellType];
Make sure the internals are as known as possible.
ExpansionKnown:
PROC [ct: CellType]
RETURNS [known:
BOOL];
Do we know how this cell type is decomposed?
AssertionOp: TYPE = {ignore, report, check, establish};
MerelyCheckableAssertionOp: TYPE = AssertionOp [ignore .. check];
FailableAssertionOp: TYPE = AssertionOp [report .. check];
CheckDesign: PROC [design: Design, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp];
CheckCellType: PROC [ct: CellType, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL ← TRUE];
CheckCellTypes: PROC [cts: ConstSet--of CellType--, rep, norm: AssertionOp, comparable: MerelyCheckableAssertionOp, interface, internals, instances: BOOL ← TRUE];
NoteChange: PROC [cellType: CellType];
AddPort:
PROC [p: PortPrivate ← []]
RETURNS [port: Port];
Adds as last child of parent, if any.
FullyAddPort:
PROC [p: PortPrivate ← [], andReportConnectionTo: CellInstance ←
NIL]
RETURNS [port: Port, connection: Wire ←
NIL];
Adds dummy wires by instances and groups in arrays.
RemovePort: PROC [port: Port];
AddEdge:
PROC [vs:
ARRAY GraphDirection
OF Vertex, port: Port];
Edge for port.prev (if that's not NIL) must already be present.
AddEdges:
PROC [vs:
ARRAY GraphDirection
OF Vertex, port: Port];
Will introduce Intermediaries, if necessary.
RemoveEdge: PROC [e: Edge];
RemoveEdges:
PROC [e: Edge];
Removes ancestor Intermediaries that have no children.
UnlinkPort:
PROC [ci: CellInstance, port: Port];
Remove the edge for given port, which must be immediately connected.
UnlinkPorts:
PROC [ci: CellInstance, ports: ConstSet
--of Port--];
Remove the edges for given ports, which need not be immediately connected.
Instantiate: PROC [type, containingCT: CellType, names: ListData ← noListData, other: Assertions ← NIL] RETURNS [ci: CellInstance];
PortForWire:
PROC [ct: CellType, internal: Wire, ci: CellInstance, mayAdd:
BOOL]
RETURNS [port: Port, external: Wire];
If ci#NIL, ci.port is connected to external.
FullyInstantiate:
PROC [type, containingCT: CellType, names: ListData ← noListData, other: Assertions ←
NIL]
RETURNS [ci: CellInstance];
Adds dummy wires.
CreateWire:
PROC [containingCT: CellType, containingWire: Wire ←
NIL, names: ListData ← noListData, other: Assertions ←
NIL, copy: Wire ←
NIL]
RETURNS [w: Wire];
As last child of containingWire, if any.
With same structure as copy, if given, leaf structure otherwise.
CreateIntermediary: PROC [from: Vertex, go: GraphDirection, containingCT: CellType, port: Port, names: ListData ← noListData, other: Assertions ← NIL] RETURNS [im: Intermediary];
CreateCellType: PROC [design: Design, cellTypeName: ROPE, class: CellClass, inheritNames, internals: BOOL, otherPublic, otherPrivate: Assertions ← NIL] RETURNS [ct: CellType];
CreateArray: PROC [design: Design, cellTypeName: ROPE, class: CellClass, eltType: CellType, size2, basePeriod: Size2, inheritNames: BOOL, otherPublic, otherPrivate: Assertions ← NIL] RETURNS [ct: CellType];
CrossNames: PROC [outer, inner: Set--of SteppyName--] RETURNS [ListData];
FetchVertex: PROC [ct: CellType, name: SteppyName] RETURNS [Vertex];
KnowVertexName: PROC [v: Vertex, name: SteppyName];
ForgetVertexName: PROC [v: Vertex, name: SteppyName];
IndexVertexNames: PROC [v: Vertex, names: Set ← Sets.nilSet];
UnindexVertexNames: PROC [v: Vertex];
KnowPortName:
PROC [p: Port, name: SteppyName]
RETURNS [new:
BOOL]
~ INLINE {new ← p.PortNames.AddElt[SnV[name]]};
ForgetPortName:
PROC [p: Port, name: SteppyName]
RETURNS [knew:
BOOL]
~ INLINE {knew ← p.PortNames.RemElt[SnV[name]]};
NoteLevelChange: PROC [w: Wire];
DeleteVertex: PROC [v: Vertex];
IsMirror: PROC [v: CellInstance] RETURNS [isMirror: BOOL];
AddMirror: PROC [CellType];
MergeNets: PROC [net1, net2: Wire] RETURNS [merged, doomed: Wire];
GroupWires:
PROC [sibs: Seq
--of wire--, parentNames: ListData]
RETURNS [parent: Wire];
The sibs must all be siblings; the parent is introduced in their place and the siblings are moved below the parent. Graph connections are fixed up.
GroupPorts: PROC [sibs: Seq--of port--, parentNames: ListData] RETURNS [parent: Port];
ExpandName: PROC [fileName, defaultExtension: ROPE] RETURNS [fullFName: ROPE, cp: FS.ComponentPositions];
ParseSteppyName: PROC [raw: ROPE] RETURNS [SteppyName];
UnparseSteppyName: PROC [s: SteppyName] RETURNS [ROPE];
Log: PROC [fmt: ROPE, args: LORA ← NIL];
PrintOnLog: PROC [REF ANY];
END.