LichenData2Impl.Mesa
Last tweaked by Mike Spreitzer on February 2, 1988 1:18:42 pm PST
DIRECTORY AbSets, AMBridge, Asserting, Basics, BiRels, Convert, FS, GList, Interpreter, InterpreterOps, IntHashTable, IntStuff, IO, LichenArrayStuff, LichenDataOps, LichenDataStructure, LichenNavigation, LichenPrinting, List, ProcessProps, Rope, SetBasics, StructuredStreams, SymTab, TiogaAccess, UnparserBuffer, ViewerIO;
LichenData2Impl:
CEDAR
PROGRAM
IMPORTS AbSets, AMBridge, Asserting, BiRels, Convert, FS, InterpreterOps, IntStuff, IO, LichenArrayStuff, LichenDataOps, LichenDataStructure, LichenNavigation, List, ProcessProps, Rope, SetBasics, StructuredStreams, SymTab, TiogaAccess, UnparserBuffer
EXPORTS LichenArrayStuff, LichenDataStructure, LichenDataOps, LichenPrinting
=
BEGIN OPEN LichenDataOps, LichenPrinting, LichenArrayStuff, LichenDataStructure, Sets:AbSets, Ints:IntStuff, SS:StructuredStreams, UB:UnparserBuffer;
DimName: ARRAY Dim OF ROPE = [Foo: "Foo", Bar: "Bar"];
step: ROPE = ".";
Describe:
PUBLIC
PROC [subject:
REF
ANY, relativeTo:
REF
ANY ←
NIL, nameGen: NameGenerator ←
NIL]
RETURNS [name:
ROPE] = {
name ← UnparseSteppyName[SteppyDescribe[subject, relativeTo, nameGen]];
RETURN};
SteppyDescribe:
PUBLIC
PROC [subject:
REF
ANY, relativeTo:
REF
ANY ←
NIL, nameGen: NameGenerator ←
NIL]
RETURNS [name: SteppyName] = {
GetShort:
PROC [oldAssns: Assertions]
RETURNS [newAssns: Assertions, name:
ROPE] = {
name ← NARROW[Asserting.FnVal[nameReln, newAssns ← oldAssns]];
IF name =
NIL
THEN {
name ← nameGen.GenerateName[nameGen.data, subject];
WITH subject
SELECT
FROM
v: Vertex => KnowVertexName[v, LSn[LIST[name]]];
ENDCASE => newAssns ← Asserting.Assert1[nameReln, name, newAssns];
name ← name};
RETURN};
IF nameGen = NIL THEN nameGen ← defaultNameGen;
IF subject = relativeTo
THEN name ← noName
ELSE
WITH subject
SELECT
FROM
d: Design => {
short: ROPE;
[d.other, short] ← GetShort[d.other];
name ← LSn[LIST[short]];
RETURN};
ct: CellType => {
short: ROPE;
[ct.otherPublic, short] ← GetShort[ct.otherPublic];
name ← LSn[LIST[short]];
IF ct.designs.HasMemA[relativeTo] OR ct.designs.Empty THEN NULL ELSE name ← SNCat[SteppyDescribe[GetADesign[ct], relativeTo, nameGen], name];
RETURN};
v: Vertex => {
parent: REF ANY;
IF v.VertexNames.Empty THEN KnowVertexName[v, name ← LSn[LIST[nameGen.GenerateName[nameGen.data, subject]]]] ELSE name ← VSn[v.VertexNames.First[].Val];
WITH v
SELECT
FROM
ci: CellInstance => parent ← v.containingCT;
im: Intermediary => parent ← ImParent[im];
w: Wire => parent ← WireContainer[w];
ENDCASE => ERROR;
IF relativeTo#parent AND parent#NIL THEN name ← SNCat[SteppyDescribe[parent, relativeTo, nameGen], name];
RETURN};
port: Port => {
parent: REF ANY ~ port.parent;
IF port.PortNames.Empty THEN [] ← KnowPortName[port, name ← LSn[LIST[nameGen.GenerateName[nameGen.data, subject]]]] ELSE name ← VSn[port.PortNames.First[].Val];
IF relativeTo#parent AND parent#NIL THEN name ← SNCat[SteppyDescribe[parent, relativeTo, nameGen], name];
RETURN};
ENDCASE => ERROR;
};
GetADesign:
PROC [ct: CellType]
RETURNS [d: Design] = {
RETURN [NARROW[ct.designs.AnElt[].MDA]]};
WireContainer:
PROC [w: Wire]
RETURNS [container:
REF
ANY] = {
container ←
SELECT w.containingWire
FROM
NIL => w.containingCT,
ENDCASE => w.containingWire;
};
genBland: NameGenerator =
NEW [NameGeneratorPrivate ← [
GenerateBlandName,
NEW [NameCountsPrivate ← []]
]];
NameCounts: TYPE = REF NameCountsPrivate;
NameCountsPrivate:
TYPE =
RECORD [
design, cellType, port, vertex: INT ← 0
];
GenerateBlandName:
PROC [data, subject:
REF
ANY]
RETURNS [name:
ROPE] = {
nc: NameCounts = NARROW[data];
name ← GenByCount[nc, "#", subject];
};
GenByCount:
PROC [nc: NameCounts, sep:
ROPE, subject:
REF
ANY]
RETURNS [name:
ROPE] = {
n: INT ← 0;
WITH subject
SELECT
FROM
d: Design => {n ← nc.design ← nc.design + 1; name ← "D"};
ct: CellType => {n ← nc.cellType ← nc.cellType + 1; name ← "CT"};
p: Port => {n ← nc.port ← nc.port + 1; name ← "P"};
v: Vertex => {n ← nc.vertex ← nc.vertex + 1; name ← "V"};
ENDCASE => ERROR;
name ← name.Cat[sep, Convert.RopeFromInt[n]];
};
genSymbol: NameGenerator =
NEW [NameGeneratorPrivate ← [
GenerateSymbolName,
NEW [TVNameGeneratorPrivate ← [
nc: NEW [NameCountsPrivate ← []],
symbols: LIST[SymTab.Create[]]
]]
]];
TVNameGenerator: TYPE = REF TVNameGeneratorPrivate;
TVNameGeneratorPrivate:
TYPE =
RECORD [
nc: NameCounts,
symbols: Interpreter.SymbolsList
];
GenerateSymbolName:
PROC [data, subject:
REF
ANY]
RETURNS [name:
ROPE] = {
tvng: TVNameGenerator ~ NARROW[data];
evalHead: InterpreterOps.EvalHead ~ NARROW[List.Assoc[$EvalHead, ProcessProps.GetPropList[]]];
syms: Interpreter.SymbolsList ~ IF evalHead#NIL AND evalHead.specials#NIL THEN evalHead.specials ELSE tvng.symbols;
name ← Rope.Concat[IF syms=tvng.symbols THEN "&&" ELSE "&", GenByCount[tvng.nc, "", subject]];
TRUSTED {InterpreterOps.RegisterTV[
name: name,
tv: AMBridge.TVForReferent[
WITH subject
SELECT
FROM
d: Design => NEW [Design ← d],
ct: CellType => NEW [CellType ← ct],
p: Port => NEW [Port ← p],
v: Vertex => NEW [Vertex ← v],
ENDCASE => ERROR],
symbolsList: syms]};
RETURN};
defaultNameGen: NameGenerator ~ genSymbol;
PrintObject:
PROC [to:
IO.
STREAM, united:
BOOL,
PrintIt:
PROC] = {
SS.Bp[to, IF united THEN united ELSE lookLeft, printStep];
SS.Begin[to];
PrintIt[!UNWIND => SS.End[to]];
SS.End[to];
};
PrintRope:
PROC [to:
IO.
STREAM, united:
BOOL, rope:
ROPE] = {
SS.Bp[to, IF united THEN united ELSE lookLeft, printStep];
SS.Begin[to];
to.PutRope[rope !UNWIND => SS.End[to]];
SS.End[to];
};
printStep: INT ← 2;
printWidth: INT ← 76;
PrintDesignOnFile:
PUBLIC
PROC [design: Design, nameGen: NameGenerator ←
NIL, fileName:
ROPE ←
NIL, tioga:
BOOL ←
FALSE, pacify:
IO.
STREAM ←
NIL,
Filter: CellTypeFilter ←
NIL] = {
realFileName: ROPE = IF fileName # NIL THEN fileName ELSE Rope.Cat[Describe[design], ".design"];
ss, fs: IO.STREAM;
taw: TiogaAccess.Writer;
IF tioga
THEN {
taw ← TiogaAccess.Create[];
ss ← SS.Create[UB.NewInittedHandle[[output: [access[taw, printStep]], margin: printWidth]]];
}
ELSE {
fs ← FS.StreamOpen[fileName: realFileName, accessOptions: create, keep: 10];
ss ← SS.Create[UB.NewInittedHandle[[output: [stream[fs]], margin: printWidth]]];
};
PrintDesignSubset[ss, design, nameGen, pacify, Filter];
IF tioga THEN TiogaAccess.WriteFile[taw, realFileName] ELSE IO.Close[fs];
ss.Close[];
};
PrintDesign:
PUBLIC
PROC [to:
IO.
STREAM, design: Design, nameGen: NameGenerator ←
NIL, pacify:
IO.
STREAM ←
NIL] = {
PrintDesignSubset[to, design, nameGen, pacify, NIL];
};
PrintDesignSubset:
PUBLIC
PROC [to:
IO.
STREAM, design: Design, nameGen: NameGenerator ←
NIL, pacify:
IO.
STREAM ←
NIL,
Filter: CellTypeFilter ←
NIL] = {
n: NAT ← 0;
CTPrint:
PROC [ra: Sets.Value] = {
ct: CellType = NARROW[ra.VA];
Inner:
PROC = {
IF pacify#NIL THEN pacify.PutF["%g: %g ", [integer[n ← n+1]], [rope[Describe[ct, design, nameGen]]]];
PrintCellType[to, ct, nameGen];
IF pacify#NIL THEN pacify.PutRope[" .\n"];
};
IF Filter=NIL OR Filter[ct] THEN PrintObject[to, TRUE, Inner];
};
IF pacify#NIL AND Filter=NIL THEN pacify.PutF["Total: %g\n", [integer[design.cellTypes.Size.EN]]];
IF NOT SS.IsAnSS[to] THEN to ← SS.Create[UB.NewInittedHandle[[output: [stream[to]], margin: printWidth]]];
to.PutF["%g: Design {", [rope[Describe[design, NIL, nameGen]]]];
design.cellTypes.Enumerate[CTPrint];
to.PutF["}"];
};
PrintNameAndAliases:
PROC [to:
IO.
STREAM, name:
ROPE, names: Set
--of SteppyName--] ~ {
first, second: BOOL ← TRUE;
PerName:
PROC [val: Sets.Value] ~ {
name: SteppyName ~ VSn[val];
IF first
THEN first ←
FALSE
ELSE {
IF second THEN second ← FALSE ELSE to.PutRope[","];
SS.Bp[to, width, printStep, " "];
to.PutRope[UnparseSteppyName[name]];
};
RETURN};
to.PutRope[name];
IF names.Size[Ints.two].Compare[Ints.one]>equal
THEN {
to.PutRope["(a.k.a."];
names.Enumerate[PerName];
to.PutRope[")"];
};
RETURN};
PrintCellType:
PUBLIC
PROC [to:
IO.
STREAM, ct: CellType, nameGen: NameGenerator ←
NIL] = {
PortPrint:
PROC = {
to.PutF["port: "];
PrintPort[to, ct.port, nameGen];
};
IWPrint:
PROC = {
to.PutF["internal wire: "];
PrintWire[to, ct.asUnorganized.internalWire, nameGen];
};
CIPrint:
PROC = {
to.PutF["contained instances: "];
PrintInstances[to, ct.asUnorganized.containedInstances, ct.asUnorganized.mirror, nameGen];
};
AyPrint:
PROC = {
to.PutRope["asArray: "];
PrintArray[to, ct, nameGen]
};
IF NOT SS.IsAnSS[to] THEN to ← SS.Create[UB.NewInittedHandle[[output: [stream[to]], margin: printWidth]]];
to.PutRope[Describe[ct, GetADesign[ct], nameGen]];
to.PutRope[": CellType["];
PrintObject[to, TRUE, PortPrint];
IF ct.asUnorganized #
NIL
THEN {
to.PutRope[", "]; PrintObject[to, TRUE, IWPrint];
to.PutRope[", "]; PrintObject[to, TRUE, CIPrint];
};
IF ct.asArray #
NIL
THEN {
to.PutRope[", "]; PrintObject[to, TRUE, AyPrint];
};
to.PutRope["]"];
};
limitPort: BOOL ← TRUE;
portLimit: NAT ← 69;
MaybePrintSeq:
PROC [to:
IO.
STREAM, parent:
REF
ANY, toKids: Function
--parent
b Seq of child--, toName: Function
--child
b SteppyName--]
RETURNS [did:
BOOL] ~ {
kids: Seq--of child-- ~ BiRels.DeRef[toKids.ApplyA[parent].MA];
bounds: Ints.Interval ~ kids.GetIntDom[];
is: BOOL ← TRUE;
FOR i:
INT
IN [bounds.min .. bounds.max]
DO
child: REF ANY ~ kids.ApplyI[i].MDA;
IF child=NIL THEN EXIT;
{name: SteppyName ~ VSn[toName.ApplyA[child].DVal[noNameVal]];
IF name.steps#
NIL
AND name.steps.rest=
NIL
THEN
WITH name.steps.first
SELECT
FROM
x:
REF
INT =>
IF x^ = i
THEN {
grandKids: Seq ~ BiRels.DeRef[toKids.ApplyA[child].MA];
IF grandKids.Empty THEN LOOP;
};
x: ROPE => NULL;
ENDCASE => ERROR;
EXIT;
};
REPEAT
FINISHED => {
IF bounds.min=0
THEN to.PutF["*%g", [integer[bounds.max+1]]]
ELSE to.PutF["*%g..%g", [integer[bounds.min]], [integer[bounds.max]]];
RETURN [TRUE]};
ENDLOOP;
RETURN [FALSE]};
PrintPort:
PUBLIC
PROC [to:
IO.
STREAM, port: Port, nameGen: NameGenerator ←
NIL] = {
first: BOOL ← TRUE;
i: INT ← 0;
PrintNameAndAliases[to, Describe[port, port.parent, nameGen], port.PortNames];
IF port.FirstChildPort[] = NIL THEN RETURN;
IF MaybePrintSeq[to, port, LichenNavigation.portToChildren, LichenNavigation.bestPortShortName] THEN RETURN;
to.PutRope["["];
FOR subPort: Port ← port.FirstChildPort[], subPort.NextChildPort[]
WHILE subPort#
NIL
DO
PortPrint: PROC = {PrintPort[to, subPort, nameGen]};
PrintElipsis: PROC = {to.PutF["..%g.., ", [integer[i-portLimit]]]};
IF (
NOT limitPort)
OR i < portLimit
OR subPort.NextChildPort[] =
NIL
THEN {
IF first THEN first ← FALSE ELSE to.PutRope[", "];
IF limitPort AND i > portLimit THEN PrintObject[to, FALSE, PrintElipsis];
PrintObject[to, FALSE, PortPrint]
};
i ← i + 1;
ENDLOOP;
to.PutRope["]"];
};
PrintWire:
PUBLIC
PROC [to:
IO.
STREAM, wire: Wire, nameGen: NameGenerator ←
NIL] = {
first: BOOL ← TRUE;
PrintNameAndAliases[to, Describe[wire, WireContainer[wire], nameGen], wire.VertexNames];
IF wire.FirstChildWire[] = NIL THEN RETURN;
IF MaybePrintSeq[to, wire, LichenNavigation.wireToChildren, LichenNavigation.bestVertexShortName] THEN RETURN;
to.PutRope["["];
FOR subWire: Wire ← wire.FirstChildWire[], subWire.NextChildWire[]
WHILE subWire #
NIL
DO
WirePrint: PROC = {PrintWire[to, subWire, nameGen]};
IF first THEN first ← FALSE ELSE to.PutRope[", "];
PrintObject[to, FALSE, WirePrint];
ENDLOOP;
to.PutRope["]"];
};
PrintInstances:
PUBLIC
PROC [to:
IO.
STREAM, set: Set
--OF CellInstance--, mirror: CellInstance, nameGen: NameGenerator ←
NIL] = {
first: BOOL ← TRUE;
PrintIt:
PROC [val:
REF
ANY] = {
ci: CellInstance = NARROW[val];
IPrint: PROC = {PrintInstance[to, ci, nameGen]};
IF first THEN first ← FALSE ELSE to.PutRope[", "];
PrintObject[to, TRUE, IPrint];
};
to.PutRope["["];
set.EnumA[PrintIt];
IF printMirror THEN PrintIt[mirror];
to.PutRope["]"];
};
printMirror: BOOL ← TRUE;
PrintInstance:
PUBLIC
PROC [to:
IO.
STREAM, ci: CellInstance, nameGen: NameGenerator ←
NIL] = {
PrintConnections:
PROC [v: Vertex] = {
first: BOOL ← TRUE;
PrintConnection:
PROC [port: Port, w: Vertex] = {
CPrint:
PROC = {
to.PutRope[Describe[port, port.parent, nameGen]];
to.PutRope[": "];
WITH w
SELECT
FROM
im: Intermediary => {
subbing, first, allSame: BOOL ← TRUE;
wi, pi, num: INT ← 0;
parent, theOne: Wire ← NIL;
TestConnection:
PROC [p: Port, u: Vertex] ~ {
ow: Wire ~
WITH u
SELECT
FROM
x: Wire => x,
x: Intermediary => NIL,
x: CellInstance => ERROR,
ENDCASE => ERROR;
IF ow=NIL THEN subbing ← FALSE;
IF allSame
THEN {
IF ow=NIL THEN allSame ← FALSE
ELSE IF theOne=NIL THEN theOne ← ow
ELSE IF theOne#ow THEN allSame ← FALSE};
num ← num+1;
IF NOT subbing THEN RETURN;
{pn: SteppyName ~ VSn[p.PortNames.First.DVal[noNameVal]];
IF pn.grade.subs=1
AND pn.grade.nonsubs=0
THEN
WITH pn.steps.first
SELECT
FROM
x:
REF
INT => {
wn: SteppyName ~ VSn[ow.VertexNames.First.DVal[noNameVal]];
IF wn.grade.subs=1
AND wn.grade.nonsubs=0
THEN
WITH wn.steps.first
SELECT
FROM
y:
REF
INT =>
IF first
THEN {wi ← y^; pi ← x^; first ← FALSE; parent ← ow.containingWire; RETURN}
ELSE {IF y^ = (wi ← wi+1) AND x^ = (pi ← pi+1) AND parent=ow.containingWire THEN RETURN};
y: ROPE => NULL;
ENDCASE => ERROR;
};
x: ROPE => NULL;
ENDCASE => ERROR;
subbing ← FALSE;
RETURN}};
EnumerateImmediateConnections[im, TestConnection, [cellward: FALSE, wireward: TRUE]];
IF subbing THEN to.PutF["%g[%g..%g]", [rope[Describe[parent, ci.containingCT.asUnorganized.internalWire, nameGen]]], [integer[wi+1-num]], [integer[wi]]]
ELSE IF allSame AND theOne#NIL THEN to.PutF["%g*%g", [integer[num]], [rope[Describe[theOne, ci.containingCT.asUnorganized.internalWire, nameGen]]]]
ELSE PrintConnections[im];
};
wire: Wire => {
to.PutRope[Describe[wire, ci.containingCT.asUnorganized.internalWire, nameGen]];
};
ci: CellInstance => ERROR;
ENDCASE => ERROR;
};
IF first THEN first ← FALSE ELSE to.PutRope[", "];
PrintObject[to, FALSE, CPrint];
};
to.PutRope["["];
EnumerateImmediateConnections[v, PrintConnection, [cellward: FALSE, wireward: TRUE]];
to.PutRope["]"];
};
PrintNameAndAliases[to, Describe[ci, ci.containingCT, nameGen], ci.VertexNames];
to.PutF[": %g", [rope[Describe[ci.type, GetADesign[ci.type], nameGen]]] ];
PrintConnections[ci];
};
Array: TYPE ~ LichenDataStructure.Array;
printStatRep: BOOL ← TRUE;
printDumbRep: BOOL ← FALSE;
PrintArray:
PUBLIC
PROC [to:
IO.
STREAM, ct: CellType, nameGen: NameGenerator ←
NIL] = {
a: Array = ct.asArray;
groupName: VarFunction = BiRels.CreateHashFn[];
nGroups: NAT ← 0;
BasePrint:
PROC = {
to.PutF["base period = [%g, %g]", [integer[a.basePeriod[Foo]]], [integer[a.basePeriod[Bar]]]]};
StatPrint:
PROC = {
to.PutRope["static graph = ["];
PrintStatRep[to, a, nameGen];
to.PutRope["]"];
};
to.PutF["{%g BY %g OF %g, ",
[integer[a.size2[Foo]]], [integer[a.size2[Bar]]],
[rope[Describe[a.eltType, GetADesign[ct], nameGen]]]
];
PrintObject[to, FALSE, BasePrint];
IF printStatRep
THEN {
to.PutRope[", "];
PrintObject[to, TRUE, StatPrint];
};
IF printDumbRep THEN ERROR nyet;
to.PutRope["}"];
};
PrintStatRep:
PROC [to:
IO.
STREAM, a: Array, nameGen: NameGenerator] ~ {
firstEdge: BOOL ← TRUE;
PrintEdge:
PROC [val:
REF
ANY] ~ {
se: StatEdge ~ NARROW[val];
IF firstEdge THEN firstEdge ← FALSE ELSE to.PutRope[", "];
PrintRope[to, TRUE, FmtStatEdge[se, a, nameGen]];
RETURN};
a.statrep.edges.EnumA[PrintEdge, fwd];
RETURN};
FmtStatEdge:
PUBLIC
PROC [se: StatEdge, a: Array ←
NIL, nameGen: NameGenerator ←
NIL]
RETURNS [
ROPE] ~ {
Fmt:
PROC [b:
BOOL]
RETURNS [ans:
ROPE] ~ {
ep: Port ~ se.vs[b].port;
ans ← Describe[ep, PortCCT[ep].port, nameGen];
IF a=NIL OR a.basePeriod#ALL[1] THEN ans ← ans.Concat[Rope.Cat["@<", Convert.RopeFromInt[se.vs[b].phase[Foo]], ",", Convert.RopeFromInt[se.vs[b].phase[Bar]], ">"]];
RETURN};
RETURN Rope.Cat[Fmt[FALSE], " -> ", Fmt[TRUE], " by ", FmtInt2[a, se.d]]};
FmtRange2:
PROC [a: Array, r: Range2]
RETURNS [asRope:
ROPE] = {
RETURN [
SELECT
TRUE
FROM
a.size2[Bar]=1 => FmtRange[r[Foo]],
a.size2[Foo]=1 => FmtRange[r[Bar]],
ENDCASE => FmtRange[r[Foo]].Cat[":", FmtRange[r[Bar]]]
]};
FmtRange:
PUBLIC
PROC [r: Range]
RETURNS [asRope:
ROPE] = {
asRope ← Convert.RopeFromInt[r.min];
IF r.min+1 # r.maxPlusOne THEN asRope ← asRope.Cat["~", Convert.RopeFromInt[r.maxPlusOne-1]];
};
FmtInt2:
PROC [a: Array, i2: Int2]
RETURNS [
ROPE] ~ {
RETURN [
SELECT
TRUE
FROM
a=NIL => IO.PutFR["<%g, %g>", [integer[i2[Foo]]], [integer[i2[Bar]]]],
a.size2[Bar]=1 => Convert.RopeFromInt[i2[Foo]],
a.size2[Foo]=1 => Convert.RopeFromInt[i2[Bar]],
ENDCASE => IO.PutFR["<%g, %g>", [integer[i2[Foo]]], [integer[i2[Bar]]]]
]};
IsArray: PROC [ct: CellType] RETURNS [pass: BOOL] = {pass ← ct.asArray # NIL};
Is1D:
PROC [ct: CellType]
RETURNS [
BOOL]
~ {RETURN [ct.asArray#NIL AND (ct.asArray.size2[Foo]=1 OR ct.asArray.size2[Bar]=1)]};
Is2D:
PROC [ct: CellType]
RETURNS [
BOOL]
~ {RETURN [ct.asArray#NIL AND ct.asArray.size2[Foo]#1 AND ct.asArray.size2[Bar]#1]};
PrintArrays:
PROC [to:
IO.
STREAM, design: Design, nameGen: NameGenerator ←
NIL, pacify:
IO.
STREAM ←
NIL] = {
PrintDesignSubset[to, design, nameGen, pacify, IsArray];
};
PrintIncompletes:
PROC [to:
IO.
STREAM, design: Design, nameGen: NameGenerator ←
NIL, pacify:
IO.
STREAM ←
NIL] = {
PrintDesignSubset[to, design, nameGen, pacify, IsIncompleteArray];
};
IndexVertexNames:
PUBLIC
PROC [v: Vertex, names: Set ← Sets.nilSet] = {
ct: CellType = v.containingCT;
pbn: VarFunction = BiRels.DeRef[Asserting.FnVal[partsByNameKey, ct.otherPrivate]].AsVar;
top:
BOOL ~
WITH v
SELECT
FROM
x: CellInstance => TRUE,
x: Intermediary => FALSE,
x: Wire => x.containingCT.asUnorganized.internalWire=x.containingWire,
ENDCASE => ERROR;
PerName:
PROC [namev: Sets.Value] ~ {
IF pbn.AddPair[[namev, AV[v]], BiRels.addIfNew].had[leftToRight]=different THEN ERROR;
};
IF pbn=BiRels.nilBiRel OR NOT top THEN RETURN;
IF names=Sets.nilSet THEN names ← v.VertexNames;
names.Enumerate[PerName];
RETURN};
UnindexVertexNames:
PUBLIC
PROC [v: Vertex] = {
ct: CellType = v.containingCT;
pbn: VarFunction = BiRels.DeRef[Asserting.FnVal[partsByNameKey, ct.otherPrivate]].AsVar;
top:
BOOL ~
WITH v
SELECT
FROM
x: CellInstance => TRUE,
x: Intermediary => FALSE,
x: Wire => x.containingCT.asUnorganized.internalWire=x.containingWire,
ENDCASE => ERROR;
PerName:
PROC [namev: Sets.Value] ~ {
IF pbn.RemPair[[namev, AV[v]]].had[leftToRight]=different THEN ERROR;
};
IF pbn=BiRels.nilBiRel OR NOT top THEN RETURN;
v.VertexNames.Enumerate[PerName];
RETURN};
FetchVertex:
PUBLIC
PROC [ct: CellType, name: SteppyName]
RETURNS [v: Vertex] ~ {
pbn: Function ~ BiRels.DeRef[Asserting.FnVal[partsByNameKey, ct.otherPrivate]];
v ← NARROW[pbn.Apply[SnV[name]].MDA];
RETURN};
KnowVertexName:
PUBLIC
PROC [v: Vertex, name: SteppyName] = {
ct: CellType = v.containingCT;
pbn: VarFunction = BiRels.DeRef[Asserting.FnVal[partsByNameKey, ct.otherPrivate]].AsVar;
top:
BOOL ~
WITH v
SELECT
FROM
x: CellInstance => TRUE,
x: Intermediary => FALSE,
x: Wire => x.containingCT.asUnorganized.internalWire=x.containingWire,
ENDCASE => ERROR;
IF top
AND pbn#BiRels.nilBiRel
THEN {
IF pbn.AddPair[[SnV[name], AV[v]]].had[leftToRight]=different THEN ERROR;
};
IF NOT v.VertexNames.AddElt[SnV[name]] THEN ERROR;
RETURN};
ForgetVertexName:
PUBLIC
PROC [v: Vertex, name: SteppyName] = {
ct: CellType = v.containingCT;
pbn: VarFunction = BiRels.DeRef[Asserting.FnVal[partsByNameKey, ct.otherPrivate]].AsVar;
last: Assertions ← NIL;
next: Assertions ← v.other;
top:
BOOL ~
WITH v
SELECT
FROM
x: CellInstance => TRUE,
x: Intermediary => FALSE,
x: Wire => x.containingCT.asUnorganized.internalWire=x.containingWire,
ENDCASE => ERROR;
IF top
AND pbn#BiRels.nilBiRel
THEN {
IF pbn.RemPair[[SnV[name], AV[v]]].had[leftToRight]#same THEN ERROR;
};
IF NOT v.VertexNames.RemElt[SnV[name]] THEN ERROR;
RETURN};
END.