DIRECTORY Basics, Commander, Core, CoreOps, IO, ICTest, Ports, Rope, TerminalIO, TestCable; TestCableImpl: CEDAR PROGRAM IMPORTS Basics, IO, CoreOps, Ports, Rope, TerminalIO EXPORTS TestCable = BEGIN groupList: ICTest.Groups; assignmentList: ICTest.Assignments; clockAName: Core.ROPE; clockBName: Core.ROPE; Init: PUBLIC PROC [groups: ICTest.Groups, assignments: ICTest.Assignments, clockA, clockB: ICTest.ROPE _ NIL] ~ { groupList _ groups; assignmentList _ assignments; IF clockA=NIL AND clockB=NIL THEN ERROR; --at least one has to be non-NIL clockAName _ clockA; clockBName _ clockB; }; TestCable: PUBLIC ICTest.TestProc = { InitDrive: PROC [wire: Core.Wire, port: Ports.Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE] --Ports.EachPortPairProc-- = { IF port#NIL THEN port.d _ force; }; EachPair: PROC [wire: Core.Wire, port: Ports.Port] RETURNS [subElements: BOOL _ TRUE, quit: BOOL _ FALSE] --Ports.EachPortPairProc-- = { SetBS: PROC[seq: Ports.BoolSequence, b: BOOL] = { FOR i: NAT IN [0..seq.size) DO seq[i] _ b; ENDLOOP; }; Cycle: PROC = { Eval[]; }; IF CoreOps.IsFullWireName[cellType.public, wire, a.name] AND a.group#0 THEN { IF port=NIL THEN SELECT rootPort.levelType FROM ls => {rootPort.ls[count] _ H; Cycle[]; rootPort.ls[count] _ L; Cycle[]}; bs => {rootPort.bs[count] _ TRUE; Cycle[]; rootPort.bs[count] _ FALSE; Cycle[]}; c => {rootPort.c _ Basics.BITSHIFT[08000h, -rootPort.fieldStart-count]; Cycle[]; rootPort.c _ 0; Cycle[]}; lc => {rootPort.lc _ Basics.DoubleShift[[lc[080000000h]], -rootPort.fieldStart-count].lc; Cycle[]; rootPort.lc _ 0; Cycle[]}; ENDCASE => ERROR ELSE SELECT port.levelType FROM l => {port.l _ H; Cycle[]; port.l _ L; Cycle[]}; b => {port.b _ TRUE; Cycle[]; port.b _ FALSE; Cycle[]}; ENDCASE => ERROR; } ELSE IF port#NIL THEN SELECT port.levelType FROM l => port.l _ L; ls => {Ports.SetLS[port.ls, L]}; b => port.b _ FALSE; bs => {SetBS[port.bs, FALSE]}; c => port.c _ 0; lc => port.lc _ 0; ENDCASE; IF CoreOps.IsFullWireName[cellType.public, wire, clockAName] OR CoreOps.IsFullWireName[cellType.public, wire, clockBName] THEN IF port=NIL THEN SELECT rootPort.levelType FROM ls => rootPort.ls[count] _ H; bs => rootPort.bs[count] _ TRUE; c => rootPort.c _ Basics.BITSHIFT[08000h, -rootPort.fieldStart-count]; lc => rootPort.lc _ Basics.DoubleShift[[lc[080000000h]], -rootPort.fieldStart-count].lc; ENDCASE => ERROR ELSE SELECT port.levelType FROM l => port.l _ H; b => port.b _ TRUE; ENDCASE => ERROR; IF port#NIL AND port.levelType#composite THEN {count _ 0; rootPort _ port} ELSE count _ count+1; }; directionality: ICTest.Directionality _ force; probe: INT _ 1; count: NAT _ 0; lastPin: NAT _ 0; a: ICTest.Assignment; rootPort: Ports.Port; help: ICTest.ROPE _ " Commands: CR: proceed b: step backward j: jump r: repeat q: quit\n"; IF clockAName=NIL AND clockBName=NIL THEN ERROR; --no clocks [] _ Ports.VisitBinding[cellType.public, p, InitDrive]; --initialize the drives a _ ["xxyyzz", 0, 0, L, AB, A, 0, 1, 1, 1]; [] _ Ports.VisitBinding[cellType.public, p, EachPair]; --bogus call to initialize the clocks TerminalIO.PutF["\n\nProbe Card Tester%g", IO.rope[help]]; FOR l: ICTest.Assignments _ assignmentList, l.rest WHILE l#NIL DO lastPin _ MAX[l.first.probeCardPin, lastPin]; ENDLOOP; WHILE probe <= lastPin DO FOR l: ICTest.Assignments _ assignmentList, l.rest WHILE l#NIL DO a _ l.first; IF a.probeCardPin = probe THEN { FOR l: ICTest.Groups _ groupList, l.rest WHILE l#NIL DO IF l.first.number=a.group THEN { directionality _ l.first.directionality; EXIT; } ENDLOOP; SELECT TRUE FROM a.group=0 => { TerminalIO.PutRope[IO.PutFR["Pin %g is unused, %g\n", IO.int[probe], IO.rope[a.name]]]; probe _ probe+1; }; directionality=acquire => { TerminalIO.PutRope[IO.PutFR["Pin %g is acquire only\n", IO.int[probe]]]; probe _ probe+1; directionality _ force; }; ENDCASE => { DO response: ICTest.ROPE _ TerminalIO.RequestRope [IO.PutFR["Ready to test pin %g, %g ...", IO.int[probe], IO.rope[a.name]]]; IF response.Length[]=0 THEN probe _ probe+1 ELSE SELECT Rope.Fetch[response] FROM 'b, 'B => { probe _ probe-1; TerminalIO.PutRope["\n"]; }; 'j, 'J => { --jump probe _ TerminalIO.RequestInt["\nJump to pin: "]; IF probe < 1 THEN probe _ 1; IF probe >LAST[ICTest.ProbeCardPin] THEN probe _ LAST[ICTest.ProbeCardPin]; GOTO MainLoop; }; 'q, 'Q => GOTO quit; 'r, 'R => probe _ probe; --redo ENDCASE => {TerminalIO.PutRope[help]; LOOP}; EXIT REPEAT MainLoop => LOOP ENDLOOP; [] _ Ports.VisitBinding[cellType.public, p, EachPair]; TerminalIO.PutRope["done\n"]; }; EXIT; }; REPEAT FINISHED => { TerminalIO.PutRope[IO.PutFR["Pin %g not found\n", IO.int[probe]]]; probe _ probe+1; }; ENDLOOP; ENDLOOP; EXITS quit => {}; }; END. &TestCableImpl.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Last Edited by: Gasbarro October 3, 1986 12:21:02 pm PDT Last Edited by: Don Curry July 13, 1987 9:59:45 am PDT Don Curry January 31, 1987 2:54:20 pm PST -- set the clock TRUE or no vector will be generated ÊN˜™Icodešœ Ïmœ1™