DIRECTORY FS, ICTest, IO, PodToTesterConfigPin, Rope, TiogaAccess; ConfiguratorWires: CEDAR PROGRAM IMPORTS FS, IO, PodToTesterConfigPin, Rope, TiogaAccess ~ BEGIN ROPE: TYPE = Rope.ROPE; nameFieldWidth: INT _ 21; FillInHeaderPins: PROC [deviceName: ROPE, assignments: ICTest.Assignments, DeviceMap: PROC [p: ICTest.ProbeCardPin] RETURNS [ICTest.DUTHeader]] RETURNS [newAssignments: ICTest.Assignments _ NIL] ~ { fName: Rope.ROPE _ Rope.Concat[deviceName, ".assignments"]; out: IO.STREAM _ FS.StreamOpen[fName, $create]; c: TiogaAccess.TiogaChar; writer: TiogaAccess.Writer; reader: TiogaAccess.Reader; revList: ICTest.Assignments; IO.PutF[out, "\n"]; IO.PutF[out, " L \n"]; IO.PutF[out, " o \n"]; IO.PutF[out, " a T \n"]; IO.PutF[out, " d e \n"]; IO.PutF[out, " s \n"]; IO.PutF[out, " B t D \n"]; IO.PutF[out, " o e U \n"]; IO.PutF[out, " a P r T \n"]; IO.PutF[out, " r o C D\n"]; IO.PutF[out, " d d h H H U\n"]; IO.PutF[out, " G B a e e T\n"]; IO.PutF[out, " r o S P B n a a \n"]; IO.PutF[out, " o a i a y n d d P\n"]; IO.PutF[out, " u r d i t e e e i\n"]; IO.PutF[out, "Signal Name p d e r e l r r n\n"]; IO.PutF[out, "----------------------------------------------------\n"]; FOR l: ICTest.Assignments _ assignments, l.rest WHILE l#NIL DO revList _ CONS[l.first, revList]; ENDLOOP; FOR l: ICTest.Assignments _ revList, l.rest WHILE l#NIL DO a: ICTest.Assignment _ l.first; IO.PutF[out, "R[[""%g"",", IO.rope[a.name]]; THROUGH [0..nameFieldWidth-Rope.Length[a.name]) DO IO.PutF[out, " "]; ENDLOOP; IO.PutF[out, "%g,", IO.int[a.group]]; IO.PutF[out, "%2g,", IO.int[a.board]]; IO.PutF[out, SELECT a.loadBoardSide FROM L=>"L,", R=>"R,", ENDCASE => ERROR]; IO.PutF[out, SELECT a.podPair FROM AB=>"AB,", CD=>"CD,", EF=>"EF,", GH=>"GH,", IJ=>"IJ,", KL=>"KL,", ENDCASE => ERROR]; IO.PutF[out, SELECT a.pod FROM A=>" A,", B=>" B,", AT=>"AT,", BT=>"BT,", ENDCASE => ERROR]; IO.PutF[out, "%g,", IO.int[a.channel]]; IF a.group#0 THEN { a.testerHeader _ l.first.testerHeader _ PodToTesterConfigPin.Map[a.loadBoardSide, a.podPair, (SELECT a.pod FROM A=>0, B=>8, AT=>16, BT=>17 ENDCASE=>ERROR)+a.channel]; }; IO.PutF[out, "%3g,", IO.int[a.testerHeader]]; IF a.group#0 THEN { a.dUTHeader _ l.first.dUTHeader _ DeviceMap[a.probeCardPin]; }; IO.PutF[out, "%3g,", IO.int[a.dUTHeader]]; IO.PutF[out, "%3g]];\n", IO.int[a.probeCardPin]]; ENDLOOP; FOR l: ICTest.Assignments _ revList, l.rest WHILE l#NIL DO newAssignments _ CONS[l.first, newAssignments]; ENDLOOP; IO.Close[out]; reader _ TiogaAccess.FromFile[fName]; writer _ TiogaAccess.Create[]; UNTIL TiogaAccess.EndOf[reader] DO c _ TiogaAccess.Get[reader]; c.looks['f] _ TRUE; TiogaAccess.Put[writer, c]; ENDLOOP; TiogaAccess.WriteFile[writer, fName]; TiogaAccess.DoneWith[reader]; }; MakeWireListForMike: PROC [deviceName: ROPE, assignments: ICTest.Assignments] ~ { fName: Rope.ROPE _ Rope.Concat[deviceName, ".wires"]; out: IO.STREAM _ FS.StreamOpen[fName, $create]; c: TiogaAccess.TiogaChar; writer: TiogaAccess.Writer; reader: TiogaAccess.Reader; a: ICTest.Assignment; IO.PutF[out, "Wire list for %g\n", IO.rope[deviceName]]; IO.PutF[out, "\n\nSort by Tester Header pins\n\n"]; IO.PutF[out, "\n\nTester DUT\n"]; IO.PutF[out, "------ ---\n"]; FOR i: ICTest.TesterHeader IN ICTest.TesterHeader DO FOR l: ICTest.Assignments _ assignments, l.rest WHILE l#NIL DO a _ l.first; IF a.testerHeader=i AND a.group#0 THEN { IO.PutF[out, "%3g %3g\n", IO.int[a.testerHeader], IO.int[a.dUTHeader]]; EXIT; }; ENDLOOP; ENDLOOP; IO.PutF[out, "\n\nSort by DUT Header pins"]; IO.PutF[out, "\n\nTester DUT\n"]; IO.PutF[out, "------ ---\n"]; FOR i: ICTest.DUTHeader IN ICTest.DUTHeader DO FOR l: ICTest.Assignments _ assignments, l.rest WHILE l#NIL DO a _ l.first; IF a.dUTHeader=i AND a.group#0 THEN { IO.PutF[out, "%3g %3g\n", IO.int[a.testerHeader], IO.int[a.dUTHeader]]; EXIT; }; ENDLOOP; ENDLOOP; IO.Close[out]; reader _ TiogaAccess.FromFile[fName]; writer _ TiogaAccess.Create[]; UNTIL TiogaAccess.EndOf[reader] DO c _ TiogaAccess.Get[reader]; c.looks['f] _ TRUE; TiogaAccess.Put[writer, c]; ENDLOOP; TiogaAccess.WriteFile[writer, fName]; TiogaAccess.DoneWith[reader]; }; END. LConfiguratorWires.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Last Edited by: Gasbarro February 4, 1987 3:18:14 pm PST Last Edited by: Louis Monier September 29, 1986 6:09:26 pm PDT Computes the wire-wrap pins for the Tester and DUT headers based on Pods, Bytes, Channels, etc. Writes out the file .assignments with the header fields filled in with the appropriate information. Also updates the assignments data structure so the MakeWireListForMike[] (see below) can be run. --make a reverse copy --print it and modify it --put it back Makes a wire list for Mike to use to wire wrap the IMS configurator board. The DUT header and Tester header fields must be filled in, in order for this proc to work. To compute these fields, use the FillInHeaderPins proc above. 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