<> <> <> <> <<>> <> <> DIRECTORY CD USING [Layer, Number, Rect], CoreGeometry USING [CellType, Decoration, Rect, Transformation, Wire], Rope USING [ROPE], TNT USING [TNT]; Drc: CEDAR DEFINITIONS ~ BEGIN Transf: TYPE ~ CoreGeometry.Transformation; CoreCell: TYPE ~ CoreGeometry.CellType; Layout: TYPE ~ CoreGeometry.Decoration; Wire: TYPE ~ CoreGeometry.Wire; Rect: TYPE ~ CoreGeometry.Rect; -- RECORD [x1, y1, x2, y2: Number]; Number = INT <> CheckDesignRules: PROC [cell: CoreCell, external: Wire, tech: Tech, viaFlatness: BOOL _ FALSE, stopFlag: REF BOOL, lap: REF CARDINAL, currentCell: REF Rope.ROPE, layout: Layout] RETURNS [quantity: CARDINAL _ 0]; < NIL. Design rule violations are flagged in the Core cell using the property DRV (Design Rule Violation) with key DRVkey = $DrcError. The property DRV is put only on cells having at least one violation.>> <> <> <> <> coreInconsistent: ERROR [reason: Rope.ROPE, torch: REF ANY]; <> DRV: TYPE ~ REF DesignRuleViolation; DRVkey: ATOM; DesignRuleViolation: TYPE ~ RECORD [count: INT _ 0, places: LIST OF ErrorRect]; ErrorRect: TYPE ~ RECORD [r: CD.Rect, msg: Rope.ROPE]; <> State: PRIVATE TYPE ~ REF StateRec; StateRec: PRIVATE TYPE ~ RECORD [ tech: Tech, -- technology dependent part nt, ttNt, ctNt: TNT.TNT, -- neighbourhood tables viaFlatness: BOOL _ FALSE, -- only for shallow cells abort: REF BOOL, -- is graceful currentCell: REF Rope.ROPE, -- for status reporting globalErrorCount: REF CARDINAL, -- the number of errors in this run anathemas: ARRAY [0 .. 9] OF CARD _ ALL [0], -- dogma violations not flagged wireCreationCount: CARD _ 1, -- for debugging attributes: CoreGeometry.Decoration]; -- key for geometry WireInstance: PRIVATE TYPE ~ RECORD [local, global: Wire, transf: Transf, gateHint: GateHint]; GateHint: PRIVATE TYPE ~ REF WireInstance _ NIL; WireSet: PRIVATE TYPE ~ REF WireSetRec; WireSetRec: PRIVATE TYPE ~ RECORD [elt: SEQUENCE size: NAT OF WireInstance]; Context: TYPE ~ RECORD [cell: CoreCell, t: Transf]; WirePairProc: PRIVATE TYPE ~ PROC [where: Context, w1, w2: WireInstance, relatedWires: REF ANY _ NIL, window: Rect, state: State]; <> <<>> WireProc: PRIVATE TYPE ~ PROC [cell: CoreCell, w: Wire, state: State]; CellProc: PRIVATE TYPE ~ PROC [cell: CoreCell, state: State]; Tech: TYPE ~ REF TechRec; TechRec: PRIVATE TYPE ~ RECORD [ checkedBy: PUBLIC ATOM, ruleTables: REF, maxSeparation, ttMaxSep, ctMaxSep: CD.Number _ LAST [CD.Number], illegalLayer: ARRAY CD.Layer OF BOOL _ ALL [TRUE], lambda: CD.Number, -- creature comfort for debugging verifyWire: WireProc, verifyWirePair: WirePairProc, verifyCell: PUBLIC CellProc _ NIL]; <> MarkError: PRIVATE PROC [obj: CoreCell, state: State, e: ErrorRect]; AtomicWireHull: PRIVATE PROC [w: WireInstance, state: State] RETURNS [h: Rect] END.