Drc.mesa
Copyright Ó 1985, 1986, 1987, 1988 by Xerox Corporation. All rights reserved.
Written by gbb, January 12, 1987 11:47:17 am PST
gbb January 22, 1988 10:08:54 am PST
Genista is the Grandson of Spinifex. It is a hierarchical design rule checker that monkeys around in a Core design and tries to find all the ChipNDale geometry in order to check as many design rules as it possibly can.
Gli uomini vollero piuttosto le tenebre che la luce (Giovanni, III, 19.)
DIRECTORY
CD USING [Layer, Number, Rect],
CoreGeometry USING [CellType, Decoration, Rect, Transformation, Wire],
Rope USING [ROPE],
TNT USING [TNT];
Drc: CEDAR DEFINITIONS ~ BEGIN
Transf: TYPE ~ CoreGeometry.Transformation;
CoreCell: TYPE ~ CoreGeometry.CellType;
Layout: TYPE ~ CoreGeometry.Decoration;
Wire: TYPE ~ CoreGeometry.Wire;
Rect: TYPE ~ CoreGeometry.Rect; -- RECORD [x1, y1, x2, y2: Number]; Number = INT
DRC
CheckDesignRules: PROC [cell: CoreCell, external: Wire, tech: Tech, viaFlatness: BOOL ← FALSE, stopFlag: REF BOOL, lap: REF CARDINAL, currentCell: REF Rope.ROPE, layout: Layout] RETURNS [quantity: CARDINAL ← 0];
cell and its subcells are verified, except the cells with property $DoNotDRC <> NIL. Design rule violations are flagged in the Core cell using the property DRV (Design Rule Violation) with key DRVkey = $DrcError. The property DRV is put only on cells having at least one violation.
The tech handle must be created using one of the technology dependent modules.
If via flatness is verified only if the appropriate toggle is set. Since Genista is hierarchical, the verification of via flatness makes sense only for shallow hierarchies of not more than three levels.
The stopFlag is tested periodically. If it is TRUE Drc stops. This parameter is required because it is the only way the client can know whether the DRC was aborted. lap and currentCell allow to inquire the status.
The return parameter quantity contains the number of errors found.
coreInconsistent: ERROR [reason: Rope.ROPE, torch: REF ANY];
Access to violations
DRV: TYPE ~ REF DesignRuleViolation;
DRVkey: ATOM;
DesignRuleViolation: TYPE ~ RECORD [count: INT ← 0, places: LIST OF ErrorRect];
ErrorRect: TYPE ~ RECORD [r: CD.Rect, msg: Rope.ROPE];
Types for writing the technology dependent part
State: PRIVATE TYPE ~ REF StateRec;
StateRec: PRIVATE TYPE ~ RECORD [
tech: Tech,   -- technology dependent part
nt, ttNt, ctNt: TNT.TNT,  -- neighbourhood tables
viaFlatness: BOOL ← FALSE,  -- only for shallow cells
abort: REF BOOL,   -- is graceful
currentCell: REF Rope.ROPE,  -- for status reporting
globalErrorCount: REF CARDINAL,  -- the number of errors in this run
anathemas: ARRAY [0 .. 9] OF CARD ← ALL [0], -- dogma violations not flagged
wireCreationCount: CARD ← 1,  -- for debugging
attributes: CoreGeometry.Decoration]; -- key for geometry
WireInstance: PRIVATE TYPE ~ RECORD [local, global: Wire, transf: Transf, gateHint: GateHint];
GateHint: PRIVATE TYPE ~ REF WireInstance ← NIL;
WireSet: PRIVATE TYPE ~ REF WireSetRec;
WireSetRec: PRIVATE TYPE ~ RECORD [elt: SEQUENCE size: NAT OF WireInstance];
Context: TYPE ~ RECORD [cell: CoreCell, t: Transf];
WirePairProc: PRIVATE TYPE ~ PROC [where: Context, w1, w2: WireInstance, relatedWires: REF ANY ← NIL, window: Rect, state: State];
w1 and w2 are the wire instances, relatedWires are those whose geometry might avoid a design rule violation at a different hierarchical level. The window is supposed to be already bloated.
WireProc: PRIVATE TYPE ~ PROC [cell: CoreCell, w: Wire, state: State];
CellProc: PRIVATE TYPE ~ PROC [cell: CoreCell, state: State];
Tech: TYPE ~ REF TechRec;
TechRec: PRIVATE TYPE ~ RECORD [
checkedBy: PUBLIC ATOM,
ruleTables: REF,
maxSeparation, ttMaxSep, ctMaxSep: CD.Number ← LAST [CD.Number],
illegalLayer: ARRAY CD.Layer OF BOOL ← ALL [TRUE],
lambda: CD.Number, -- creature comfort for debugging
verifyWire: WireProc,
verifyWirePair: WirePairProc,
verifyCell: PUBLIC CellProc ← NIL];
Semantic detail: the procedures are called in the above order. In particular, the cell procedure can assume that the wire procedure has already been called for the cell. The cell procedure is a hack circumvent inadequacies in the extraction software.
MarkError: PRIVATE PROC [obj: CoreCell, state: State, e: ErrorRect];
AtomicWireHull: PRIVATE PROC [w: WireInstance, state: State] RETURNS [h: Rect]
END.