<> <> <> <> DIRECTORY Core, CoreClasses, IO, Sisyph, SymTab; FSM: CEDAR DEFINITIONS = BEGIN <> <> <> FSMData: TYPE = REF FSMDataRec; FSMDataRec: TYPE = RECORD [ name: IO.ROPE _ NIL, states: States _ NIL, initialState: State _ NIL, outInAll: BOOL _ TRUE, -- TRUE => all outputs avail as inputs outIns: LIST OF IO.ROPE _ NIL, -- If ~outInAll then list of outs avail as inputs register: RegisterType _ edgeTriggered, mach: Expression _ NIL, -- private assert: Expression _ NIL, -- any guaranteed conditions publics: LIST OF IO.ROPE _ NIL, -- private srcCellType: Core.CellType _ NIL ]; -- private States: TYPE = LIST OF State; State: TYPE = REF StateRec; StateRec: TYPE = RECORD [ name: IO.ROPE _ NIL, outputs: LIST OF IO.ROPE _ NIL, -- Moore state and outs, Mealy state outputsInv: LIST OF IO.ROPE _ NIL, -- explicit control of state encodings outTrans: Transitions _ NIL, inTrans: Transitions _ NIL, -- private srcCellInst: CellInstance _ NIL ]; -- private Transitions: TYPE = LIST OF Transition; Transition: TYPE = REF TransitionRec; TransitionRec: TYPE = RECORD [ enable: Expression _ NIL, outputs: LIST OF IO.ROPE _ NIL, -- Mealy outs target: State _ NIL, srcCellInst: CellInstance _ NIL ]; -- private Expression: TYPE = REF; CellInstance: TYPE = CoreClasses.CellInstance; RegisterType: TYPE = {edgeTriggered, twoPhase, none}; <> Context: TYPE = REF ContextRec; ContextRec: TYPE = RECORD[ fsm: FSMData, logic: LIST OF CurrentLogic, data: LIST OF CurrentData, state: IO.ROPE, declares: LIST OF Declaration, -- Used during declarations signals: Signals, -- Used after all declarations invTab: SymTab.Ref, stateTab: SymTab.Ref ]; CurrentLogic: TYPE = LIST OF FieldValMask _ NIL; CurrentData: TYPE = LIST OF FieldValMask _ NIL; FieldValMask: TYPE = RECORD[f,v,m: NAT _ default]; Signals: TYPE = REF SignalSeqRec; SignalSeqRec: TYPE = RECORD [SEQUENCE size: NAT OF Declaration]; Declaration: TYPE = RECORD [name: IO.ROPE, io: InOut, size: NAT, index: NAT]; InOut: TYPE = {in, out, outIn}; -- outIn = clocked state variables, prev val input default: NAT = LAST[NAT]; <> CodeMachine: PROC [fsm: FSMData, exprImplKey: ATOM _ $SC] RETURNS [ct: Core.CellType]; <> SchStateCell: PROC RETURNS [ct: Core.CellType]; -- Target Source SchTransitionCell: PROC RETURNS [ct: Core.CellType]; -- Source Target SchMachine: PROC [ cx: Sisyph.Context, name: IO.ROPE _ NIL, register: RegisterType _ edgeTriggered, exprImplKey: ATOM _ $SC ] RETURNS [ct: Core.CellType]; <> <> <> <> <> <<"Vdd", "Gnd", "Reset",>> <> <> <> < "Clock">> < "PhA", "PhB">> < 'Nxt' prepended to all outputs which are also inputs,>> <> <> <> <> <> << or maybe state outs: ctx.IfState[NIL]; ctx.AddOut[id, val]; ctx.SetState["state"]; ...>> <> <<>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<>> <<>> Create: PROC[name: IO.ROPE] RETURNS[ctx: Context]; Declare: PROC[ctx: Context, name: IO.ROPE, io: InOut, size: NAT _ 1] RETURNS[ix: NAT]; IfState: PROC[ctx: Context, s: IO.ROPE]; If: PROC[ctx: Context, f, v: NAT, m: NAT _ default]; And: PROC[ctx: Context, f, v: NAT, m: NAT _ default]; AddOut: PROC[ctx: Context, f, v: NAT, m: NAT _ default]; JmpState: PROC[ctx: Context, s: IO.ROPE]; Finish: PROC[ctx: Context] RETURNS[mach: FSMData]; <> EncodeStates: PROC[fsm: FSMData]; -- multiple calls ok ConvertToExp: PROC[fsm: FSMData] RETURNS[machine: LIST OF REF]; -- calls EncodeStates <> ImplementExprFile: PROC[file: IO.ROPE, register: RegisterType, exprImplKey: ATOM] RETURNS[Core.CellType]; ImplementExpr: PROC[mach: Expression, register: RegisterType, exprImplKey: ATOM] RETURNS[Core.CellType]; BuildSCMachine: PROC[mach: Expression] RETURNS [Core.CellType]; BuildSCGates: PROC[mach: Expression] RETURNS [Core.CellType]; BuildSCRegister: PROC[mach: Expression] RETURNS [Core.CellType]; END.